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Searched refs:Reg2 (Results 1 – 25 of 41) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp669 MCRegister Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
684 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
686 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
689 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
692 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
695 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
698 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
703 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
709 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
712 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp450 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
1019 bool &HaveReg2, Register &Reg2, in parseAddress() argument
1094 if (parseIntegerRegister(Reg2, RegGR)) in parseAddress()
1098 if (parseRegister(Reg2, /*RequirePercent=*/true)) in parseAddress()
1102 Reg2.Num = 0; in parseAddress()
1103 Reg2.Group = RegGR; in parseAddress()
1104 Reg2.StartLoc = Reg2.EndLoc = Parser.getTok().getLoc(); in parseAddress()
1138 Register Reg1, Reg2; in parseAddress() local
1145 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength, in parseAddress()
1188 if (parseAddressRegister(Reg2)) in parseAddress()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.h97 unsigned Reg1, unsigned Reg2);
100 unsigned Reg1, unsigned Reg2, unsigned Reg3);
103 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
H A DMipsAsmPrinter.cpp870 unsigned Reg2) { in EmitInstrRegReg() argument
879 Reg1 = Reg2; in EmitInstrRegReg()
880 Reg2 = Temp; in EmitInstrRegReg()
884 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
890 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
894 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
901 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
905 Reg1 = Reg2; in EmitMovFPIntPair()
906 Reg2 = temp; in EmitMovFPIntPair()
909 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
H A DMicroMipsSizeReduction.cpp378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
388 if (Registers[i + 1] == Reg2) in ConsecutiveRegisters()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
H A DMips16InstrInfo.cpp275 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
286 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
290 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
H A DMips16InstrInfo.h120 unsigned Reg1, unsigned Reg2) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp195 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore() argument
198 const bool IsPaired = Reg2 != AArch64::NoRegister; in emitStore()
200 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitStore()
225 MIB.addReg(Reg2); in emitStore()
236 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad() argument
239 const bool IsPaired = Reg2 != AArch64::NoRegister; in emitLoad()
241 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitLoad()
266 MIB.addReg(Reg2, getDefRegState(true)); in emitLoad()
H A DSMEPeepholeOpt.cpp95 Register Reg2 = MI2->getOperand(3).getReg(); in isMatchingStartStopPair() local
96 if (Reg1.isPhysical() || Reg2.isPhysical() || Reg1 != Reg2) in isMatchingStartStopPair()
H A DAArch64FrameLowering.cpp3132 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateWindowsRegisterPairing() argument
3142 if (Reg2 == AArch64::FP) in invalidateWindowsRegisterPairing()
3146 if (TRI->getEncodingValue(Reg2) == TRI->getEncodingValue(Reg1) + 1) in invalidateWindowsRegisterPairing()
3154 (Reg1 - AArch64::X19) % 2 == 0 && Reg2 == AArch64::LR && !IsFirst) in invalidateWindowsRegisterPairing()
3163 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateRegisterPairing() argument
3168 return invalidateWindowsRegisterPairing(Reg1, Reg2, NeedsWinCFI, IsFirst, in invalidateRegisterPairing()
3174 return Reg2 == AArch64::LR; in invalidateRegisterPairing()
3183 unsigned Reg2 = AArch64::NoRegister; member
3191 bool isPaired() const { return Reg2 != AArch64::NoRegister; } in isPaired()
3312 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A Daarch64.cpp303 constexpr unsigned Reg2 = 9; // Holds fixup address. in lowerPointer64AuthEdgesToSigningFunction() local
375 cantFail(writeMovRegImm64Seq(AppendInstr, Reg2, in lowerPointer64AuthEdgesToSigningFunction()
379 cantFail(writePACSignSeq(AppendInstr, Reg1, ValueToSign, Reg2, Reg3, in lowerPointer64AuthEdgesToSigningFunction()
383 cantFail(writeStoreRegSeq(AppendInstr, Reg2, Reg1)); in lowerPointer64AuthEdgesToSigningFunction()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp235 MCRegister Reg2, TypeT Ty) { in getCommonMinimalPhysRegClass() argument
237 assert(Reg1.isPhysical() && Reg2.isPhysical() && in getCommonMinimalPhysRegClass()
252 RC->contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC))) in getCommonMinimalPhysRegClass()
267 MCRegister Reg1, MCRegister Reg2, MVT VT) const { in getCommonMinimalPhysRegClass() argument
268 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, VT); in getCommonMinimalPhysRegClass()
277 MCRegister Reg1, MCRegister Reg2, LLT Ty) const { in getCommonMinimalPhysRegClassLLT() argument
278 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, Ty); in getCommonMinimalPhysRegClassLLT()
H A DAggressiveAntiDepBreaker.h106 unsigned UnionGroups(MCRegister Reg1, MCRegister Reg2);
H A DMachineInstr.cpp2654 Register Reg2 = getOperand(2).getReg(); in getFirst3RegLLTs() local
2656 getRegInfo()->getType(Reg1), Reg2, in getFirst3RegLLTs()
2657 getRegInfo()->getType(Reg2)); in getFirst3RegLLTs()
2664 Register Reg2 = getOperand(2).getReg(); in getFirst4RegLLTs() local
2668 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3)); in getFirst4RegLLTs()
2676 Register Reg2 = getOperand(2).getReg(); in getFirst5RegLLTs() local
2681 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3), in getFirst5RegLLTs()
H A DTargetInstrInfo.cpp201 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
216 Reg2.isPhysical() ? MI.getOperand(Idx2).isRenamable() : false; in commuteInstructionImpl()
240 Reg0 = Reg2; in commuteInstructionImpl()
242 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
265 CommutedMI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
278 if (Reg2.isPhysical()) in commuteInstructionImpl()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCFIInstBuilder.h91 void buildRegister(MCRegister Reg1, MCRegister Reg2) const { in buildRegister() argument
94 TRI.getDwarfRegNum(Reg2, IsEH))); in buildRegister()
H A DTargetRegisterInfo.h104 bool contains(Register Reg1, Register Reg2) const { in contains() argument
107 if (!Reg1.isPhysical() || !Reg2.isPhysical()) in contains()
109 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); in contains()
356 getCommonMinimalPhysRegClass(MCRegister Reg1, MCRegister Reg2,
371 getCommonMinimalPhysRegClassLLT(MCRegister Reg1, MCRegister Reg2,
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp182 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
184 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
185 && Reg2 != OldFMAReg) { in processBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h160 unsigned SubReg1, Register Reg2, bool isKill2, unsigned SubReg2) { in addRegReg() argument
163 .addReg(Reg2, getKillRegState(isKill2), SubReg2) in addRegReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp83 unsigned Reg2);
447 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
455 .addReg(Reg2) in createRegSequence()
H A DThumb2SizeReduction.cpp758 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
761 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
763 if (Reg0 != Reg2) { in ReduceTo2Addr()
793 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
794 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.h141 MCRegister Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI);
143 MCRegister Reg2, MCOperand Op3, SMLoc IDLoc,
H A DMipsTargetStreamer.cpp238 MCRegister Reg1, MCRegister Reg2, SMLoc IDLoc, in emitRRR() argument
240 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
244 MCRegister Reg1, MCRegister Reg2, in emitRRRX() argument
251 TmpInst.addOperand(MCOperand::createReg(Reg2)); in emitRRRX()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h84 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
85 return contains(Reg1) && contains(Reg2); in contains()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp453 unsigned Reg2 = in getRegisterSeqOpValue() local
456 unsigned Binary = ((Reg1 & 0x1f) << 5) | (Reg2 - Reg1); in getRegisterSeqOpValue()

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