| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 683 unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
698 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
700 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
703 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
706 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
709 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
712 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
717 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
723 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
726 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 428 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
990 bool &HaveReg2, Register &Reg2, in parseAddress() argument
1065 if (parseIntegerRegister(Reg2, RegGR)) in parseAddress()
1068 if (isParsingATT() && parseRegister(Reg2)) in parseAddress()
1102 Register Reg1, Reg2; in parseAddress() local
1109 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength, in parseAddress()
1146 if (parseAddressRegister(Reg2)) in parseAddress()
1148 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num]; in parseAddress()
1154 if (parseAddressRegister(Reg2)) in parseAddress()
1156 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num]; in parseAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.h | 94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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| H A D | MipsAsmPrinter.cpp | 841 unsigned Reg2) { in EmitInstrRegReg() argument
850 Reg1 = Reg2; in EmitInstrRegReg()
851 Reg2 = Temp; in EmitInstrRegReg()
855 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
861 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
865 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
872 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
876 Reg1 = Reg2; in EmitMovFPIntPair()
877 Reg2 = temp; in EmitMovFPIntPair()
880 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
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| H A D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
388 if (Registers[i + 1] == Reg2) in ConsecutiveRegisters()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
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| H A D | Mips16InstrInfo.cpp | 278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
289 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
293 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
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| H A D | Mips16InstrInfo.h | 121 unsigned Reg1, unsigned Reg2) const;
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| H A D | MipsTargetStreamer.h | 133 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 205 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore() argument
208 const bool IsPaired = Reg2 != AArch64::NoRegister; in emitStore()
210 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitStore()
235 MIB.addReg(Reg2); in emitStore()
246 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad() argument
249 const bool IsPaired = Reg2 != AArch64::NoRegister; in emitLoad()
251 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitLoad()
276 MIB.addReg(Reg2, getDefRegState(true)); in emitLoad()
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| H A D | AArch64FrameLowering.cpp | 2854 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateWindowsRegisterPairing() argument
2864 if (Reg2 == AArch64::FP) in invalidateWindowsRegisterPairing()
2868 if (TRI->getEncodingValue(Reg2) == TRI->getEncodingValue(Reg1) + 1) in invalidateWindowsRegisterPairing()
2876 (Reg1 - AArch64::X19) % 2 == 0 && Reg2 == AArch64::LR && !IsFirst) in invalidateWindowsRegisterPairing()
2885 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateRegisterPairing() argument
2890 return invalidateWindowsRegisterPairing(Reg1, Reg2, NeedsWinCFI, IsFirst, in invalidateRegisterPairing()
2896 return Reg2 == AArch64::LR; in invalidateRegisterPairing()
2905 unsigned Reg2 = AArch64::NoRegister; member
2912 bool isPaired() const { return Reg2 != AArch64::NoRegister; } in isPaired()
3009 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXFMAMutate.cpp | 190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
193 && Reg2 != OldFMAReg) { in processBlock()
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| H A D | PPCVSXSwapRemoval.cpp | 899 Register Reg2 = MI->getOperand(2).getReg(); in handleSpecialSwappables() local
900 MI->getOperand(1).setReg(Reg2); in handleSpecialSwappables()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 166 unsigned Reg2, bool isKill2) { in addRegReg() argument
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 83 unsigned Reg2);
446 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
454 .addReg(Reg2) in createRegSequence()
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| H A D | Thumb2SizeReduction.cpp | 758 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
761 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
763 if (Reg0 != Reg2) { in ReduceTo2Addr()
793 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
794 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.h | 103 // Union Reg1's and Reg2's groups to form a new group.
105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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| H A D | MachineInstr.cpp | 2531 Register Reg2 = getOperand(2).getReg(); in getFirst3RegLLTs() local
2533 getRegInfo()->getType(Reg1), Reg2, in getFirst3RegLLTs()
2534 getRegInfo()->getType(Reg2)); in getFirst3RegLLTs()
2541 Register Reg2 = getOperand(2).getReg(); in getFirst4RegLLTs() local
2545 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3)); in getFirst4RegLLTs()
2553 Register Reg2 = getOperand(2).getReg(); in getFirst5RegLLTs() local
2558 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3), in getFirst5RegLLTs()
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| H A D | TargetInstrInfo.cpp | 187 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
202 Reg2.isPhysical() ? MI.getOperand(Idx2).isRenamable() : false; in commuteInstructionImpl()
208 Reg0 = Reg2; in commuteInstructionImpl()
210 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
231 CommutedMI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
244 if (Reg2.isPhysical()) in commuteInstructionImpl()
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| H A D | AggressiveAntiDepBreaker.cpp | 89 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { in UnionGroups() argument
95 unsigned Group2 = GetGroup(Reg2); in UnionGroups()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 104 bool contains(Register Reg1, Register Reg2) const { in contains() argument
107 if (!Reg1.isPhysical() || !Reg2.isPhysical()) in contains()
109 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); in contains()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/ |
| H A D | CSKYMCCodeEmitter.cpp | 270 unsigned Reg2 = in getRegSeqImmOpValue()
273 unsigned Binary = ((Reg1 & 0x1f) << 5) | (Reg2 - Reg1);
280 unsigned Reg2 = getRegisterSeqOpValue() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 227 unsigned Reg2, SMLoc IDLoc, in emitRRR() argument
229 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
233 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
239 TmpInst.addOperand(MCOperand::createReg(Reg2)); in emitRRRX()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 83 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
84 return contains(Reg1) && contains(Reg2); in contains()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCDwarf.cpp | 1335 unsigned Reg2 = Instr.getRegister2(); in emitCFIInstruction() local
1338 Reg2 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg2); in emitCFIInstruction()
1342 Streamer.emitULEB128IntValue(Reg2); in emitCFIInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 391 MCRegister Reg2; member
1099 OS << " Reg2 " << RegName(RegReg.Reg2); in print()
1188 Op->RegReg.Reg2 = Reg2No; in createRegReg()
1272 Inst.addOperand(MCOperand::createReg(RegReg.Reg2)); in addRegRegOperands()
2537 MCRegister Reg2 = matchRegisterNameHelper(Reg2Name); in parseRegReg() local
2538 if (!Reg2) in parseRegReg()
2545 Operands.push_back(RISCVOperand::createRegReg(Reg, Reg2, getLoc())); in parseRegReg()
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