Home
last modified time | relevance | path

Searched refs:Reg1 (Results 1 – 25 of 53) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp658 MCRegister Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
683 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
686 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
689 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
692 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
695 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
698 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
702 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
709 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
712 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp449 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
1018 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress() argument
1057 if (parseRegister(Reg1, /*RequirePercent=*/true)) in parseAddress()
1076 if (parseIntegerRegister(Reg1, RegGroup)) in parseAddress()
1138 Register Reg1, Reg2; in parseAddress() local
1145 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength, in parseAddress()
1160 if (parseAddressRegister(Reg1)) in parseAddress()
1162 Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num]; in parseAddress()
1176 if (parseAddressRegister(Reg1)) in parseAddress()
1182 Index = Reg1.Num == 0 ? 0 : IndexRegs[Reg1.Num]; in parseAddress()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp1316 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() local
1319 .addImm(Reg1) in InsertSEH()
1329 Register Reg1 = MBBI->getOperand(2).getReg(); in InsertSEH() local
1330 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1337 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
1367 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
1370 .addImm(Reg1) in InsertSEH()
1378 Register Reg1 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1379 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1386 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
[all …]
H A DAArch64LowerHomogeneousPrologEpilog.cpp195 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore() argument
197 assert(Reg1 != AArch64::NoRegister); in emitStore()
199 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1); in emitStore()
226 MIB.addReg(Reg1) in emitStore()
236 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad() argument
238 assert(Reg1 != AArch64::NoRegister); in emitLoad()
240 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1); in emitLoad()
267 MIB.addReg(Reg1, getDefRegState(true)) in emitLoad()
H A DSMEPeepholeOpt.cpp94 Register Reg1 = MI1->getOperand(3).getReg(); in isMatchingStartStopPair() local
96 if (Reg1.isPhysical() || Reg2.isPhysical() || Reg1 != Reg2) in isMatchingStartStopPair()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.h97 unsigned Reg1, unsigned Reg2);
100 unsigned Reg1, unsigned Reg2, unsigned Reg3);
103 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
H A DMipsAsmPrinter.cpp869 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
878 unsigned Temp = Reg1; in EmitInstrRegReg()
879 Reg1 = Reg2; in EmitInstrRegReg()
883 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
889 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
893 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
900 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
904 unsigned temp = Reg1; in EmitMovFPIntPair()
905 Reg1 = Reg2; in EmitMovFPIntPair()
908 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
H A DMips16InstrInfo.cpp275 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
284 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
288 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
289 MIB3.addReg(Reg1); in adjustStackPtrBig()
293 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
H A DMicroMipsSizeReduction.cpp378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
387 if (Registers[i] == Reg1) { in ConsecutiveRegisters()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
H A DMipsSEFrameLowering.cpp454 MCRegister Reg1 = RegInfo.getSubReg(Reg, Mips::sub_hi); in emitPrologue() local
457 std::swap(Reg0, Reg1); in emitPrologue()
460 CFIBuilder.buildOffset(Reg1, Offset + 4); in emitPrologue()
463 MCRegister Reg1 = Reg + 1; in emitPrologue() local
466 std::swap(Reg0, Reg1); in emitPrologue()
469 CFIBuilder.buildOffset(Reg1, Offset + 4); in emitPrologue()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.h136 void emitRR(unsigned Opcode, MCRegister Reg0, MCRegister Reg1, SMLoc IDLoc,
138 void emitRRX(unsigned Opcode, MCRegister Reg0, MCRegister Reg1, MCOperand Op2,
140 void emitRRR(unsigned Opcode, MCRegister Reg0, MCRegister Reg1,
142 void emitRRRX(unsigned Opcode, MCRegister Reg0, MCRegister Reg1,
145 void emitRRI(unsigned Opcode, MCRegister Reg0, MCRegister Reg1, int16_t Imm,
147 void emitRRIII(unsigned Opcode, MCRegister Reg0, MCRegister Reg1,
H A DMipsTargetStreamer.cpp210 MCRegister Reg1, SMLoc IDLoc, in emitRR() argument
212 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
226 MCRegister Reg1, MCOperand Op2, SMLoc IDLoc, in emitRRX() argument
231 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
238 MCRegister Reg1, MCRegister Reg2, SMLoc IDLoc, in emitRRR() argument
240 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
244 MCRegister Reg1, MCRegister Reg2, in emitRRRX() argument
250 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
258 MCRegister Reg1, int16_t Imm, SMLoc IDLoc, in emitRRI() argument
260 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h84 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
85 return contains(Reg1) && contains(Reg2); in contains()
717 uint16_t Reg1 = 0; variable
725 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
741 Reg0 = Reg1;
742 Reg1 = 0;
/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A Daarch64.cpp302 constexpr unsigned Reg1 = 8; // Holds pointer value to sign. in lowerPointer64AuthEdgesToSigningFunction() local
372 writeMovRegImm64Seq(AppendInstr, Reg1, ValueToSign.getValue())); in lowerPointer64AuthEdgesToSigningFunction()
379 cantFail(writePACSignSeq(AppendInstr, Reg1, ValueToSign, Reg2, Reg3, in lowerPointer64AuthEdgesToSigningFunction()
383 cantFail(writeStoreRegSeq(AppendInstr, Reg2, Reg1)); in lowerPointer64AuthEdgesToSigningFunction()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp234 getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1, in getCommonMinimalPhysRegClass() argument
237 assert(Reg1.isPhysical() && Reg2.isPhysical() && in getCommonMinimalPhysRegClass()
252 RC->contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC))) in getCommonMinimalPhysRegClass()
267 MCRegister Reg1, MCRegister Reg2, MVT VT) const { in getCommonMinimalPhysRegClass() argument
268 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, VT); in getCommonMinimalPhysRegClass()
277 MCRegister Reg1, MCRegister Reg2, LLT Ty) const { in getCommonMinimalPhysRegClassLLT() argument
278 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, Ty); in getCommonMinimalPhysRegClassLLT()
H A DMachineInstr.cpp2645 Register Reg1 = getOperand(1).getReg(); in getFirst2RegLLTs() local
2646 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1, in getFirst2RegLLTs()
2647 getRegInfo()->getType(Reg1)); in getFirst2RegLLTs()
2653 Register Reg1 = getOperand(1).getReg(); in getFirst3RegLLTs() local
2655 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1, in getFirst3RegLLTs()
2656 getRegInfo()->getType(Reg1), Reg2, in getFirst3RegLLTs()
2663 Register Reg1 = getOperand(1).getReg(); in getFirst4RegLLTs() local
2667 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1), in getFirst4RegLLTs()
2675 Register Reg1 = getOperand(1).getReg(); in getFirst5RegLLTs() local
2680 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1), in getFirst5RegLLTs()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCFIInstBuilder.h91 void buildRegister(MCRegister Reg1, MCRegister Reg2) const { in buildRegister() argument
93 nullptr, TRI.getDwarfRegNum(Reg1, IsEH), in buildRegister()
H A DTargetRegisterInfo.h104 bool contains(Register Reg1, Register Reg2) const { in contains() argument
107 if (!Reg1.isPhysical() || !Reg2.isPhysical()) in contains()
109 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); in contains()
356 getCommonMinimalPhysRegClass(MCRegister Reg1, MCRegister Reg2,
371 getCommonMinimalPhysRegClassLLT(MCRegister Reg1, MCRegister Reg2,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h159 addRegReg(const MachineInstrBuilder &MIB, Register Reg1, bool isKill1, in addRegReg() argument
161 return MIB.addReg(Reg1, getKillRegState(isKill1), SubReg1) in addRegReg()
H A DX86CompressEVEX.cpp198 Register Reg1 = Op1.getReg(); in CompressEVEXImpl() local
199 if (Reg1 == Reg0) in CompressEVEXImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp233 Register Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
256 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
270 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, in tryInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp201 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in selectInlineAsm() local
224 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in selectInlineAsm()
239 CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, T0.getValue(1)); in selectInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp365 Register Reg1 = Op1.getReg(); in legalizeCustom() local
370 MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) { in legalizeCustom()
377 Op1.setReg(convertPtrToInt(Reg1, ConvT, SpirvTy, Helper, MRI, GR)); in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp451 unsigned Reg1 = in getRegisterSeqOpValue() local
456 unsigned Binary = ((Reg1 & 0x1f) << 5) | (Reg2 - Reg1); in getRegisterSeqOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp82 const DebugLoc &DL, unsigned Reg1,
447 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
453 .addReg(Reg1) in createRegSequence()

123