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Searched refs:Reg1 (Results 1 – 25 of 50) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp672 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
697 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
700 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
703 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
706 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
709 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
712 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
716 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
723 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
726 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp1247 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() local
1250 .addImm(Reg1) in InsertSEH()
1260 Register Reg1 = MBBI->getOperand(2).getReg(); in InsertSEH() local
1261 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1268 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
1298 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
1301 .addImm(Reg1) in InsertSEH()
1309 Register Reg1 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1310 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1317 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
[all …]
H A DAArch64LowerHomogeneousPrologEpilog.cpp205 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore() argument
207 assert(Reg1 != AArch64::NoRegister); in emitStore()
209 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1); in emitStore()
236 MIB.addReg(Reg1) in emitStore()
246 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad() argument
248 assert(Reg1 != AArch64::NoRegister); in emitLoad()
250 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1); in emitLoad()
277 MIB.addReg(Reg1, getDefRegState(true)) in emitLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp427 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
989 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress() argument
1028 if (parseRegister(Reg1)) in parseAddress()
1047 if (parseIntegerRegister(Reg1, RegGroup)) in parseAddress()
1102 Register Reg1, Reg2; in parseAddress() local
1109 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength, in parseAddress()
1124 if (parseAddressRegister(Reg1)) in parseAddress()
1126 Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num]; in parseAddress()
1135 if (parseAddressRegister(Reg1)) in parseAddress()
1140 Index = Reg1.Num == 0 ? 0 : Regs[Reg1.Num]; in parseAddress()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h129 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
131 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
133 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
137 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
139 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
H A DMipsAsmPrinter.h94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
H A DMipsAsmPrinter.cpp840 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
849 unsigned Temp = Reg1; in EmitInstrRegReg()
850 Reg1 = Reg2; in EmitInstrRegReg()
854 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
860 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
864 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
871 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
875 unsigned temp = Reg1; in EmitMovFPIntPair()
876 Reg1 = Reg2; in EmitMovFPIntPair()
879 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
H A DMips16InstrInfo.cpp278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
287 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
291 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
292 MIB3.addReg(Reg1); in adjustStackPtrBig()
296 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
H A DMicroMipsSizeReduction.cpp378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
387 if (Registers[i] == Reg1) { in ConsecutiveRegisters()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
H A DMipsSEFrameLowering.cpp463 unsigned Reg1 = in emitPrologue() local
467 std::swap(Reg0, Reg1); in emitPrologue()
475 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
480 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
483 std::swap(Reg0, Reg1); in emitPrologue()
491 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
H A DMips16InstrInfo.h121 unsigned Reg1, unsigned Reg2) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp199 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
201 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
214 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
220 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
226 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
229 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
232 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX() argument
238 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
245 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
248 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
[all …]
H A DMipsMCCodeEmitter.cpp98 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1); in LowerCompactBranch()
102 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
103 if (Reg0 < Reg1) in LowerCompactBranch()
106 if (Reg0 >= Reg1) in LowerCompactBranch()
110 if (Reg1 >= Reg0) in LowerCompactBranch()
97 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1); LowerCompactBranch() local
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h83 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
84 return contains(Reg1) && contains(Reg2); in contains()
702 uint16_t Reg1 = 0; variable
710 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
726 Reg0 = Reg1;
727 Reg1 = 0;
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.cpp93 unsigned Reg1; in adjustStackPtr() local
94 loadImmediate(MBB, I, &Reg1, Amount); in adjustStackPtr()
97 .addReg(Reg1, RegState::Kill); in adjustStackPtr()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h165 unsigned Reg1, bool isKill1, in addRegReg() argument
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
H A DX86CompressEVEX.cpp198 Register Reg1 = Op1.getReg(); in CompressEVEXImpl() local
199 if (Reg1 == Reg0) in CompressEVEXImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp268 unsigned Reg1 = in getRegSeqImmOpValue()
273 unsigned Binary = ((Reg1 & 0x1f) << 5) | (Reg2 - Reg1);
278 unsigned Reg1 = getRegisterSeqOpValue() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp235 Register Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
258 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
272 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, in tryInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp347 Register Reg1 = Op1.getReg(); in legalizeCustom() local
352 MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) { in legalizeCustom()
358 Op1.setReg(convertPtrToInt(Reg1, ConvT, SpirvTy, Helper, MRI, GR)); in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp201 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in selectInlineAsm() local
224 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in selectInlineAsm()
239 CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, T0.getValue(1)); in selectInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp2522 Register Reg1 = getOperand(1).getReg(); in getFirst2RegLLTs() local
2523 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1, in getFirst2RegLLTs()
2524 getRegInfo()->getType(Reg1)); in getFirst2RegLLTs()
2530 Register Reg1 = getOperand(1).getReg(); in getFirst3RegLLTs() local
2532 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1, in getFirst3RegLLTs()
2533 getRegInfo()->getType(Reg1), Reg2, in getFirst3RegLLTs()
2540 Register Reg1 = getOperand(1).getReg(); in getFirst4RegLLTs() local
2544 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1), in getFirst4RegLLTs()
2552 Register Reg1 = getOperand(1).getReg(); in getFirst5RegLLTs() local
2557 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1), in getFirst5RegLLTs()
H A DAggressiveAntiDepBreaker.h103 // Union Reg1's and Reg2's groups to form a new group.
105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp82 const DebugLoc &DL, unsigned Reg1,
446 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
452 .addReg(Reg1) in createRegSequence()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h104 bool contains(Register Reg1, Register Reg2) const { in contains() argument
107 if (!Reg1.isPhysical() || !Reg2.isPhysical()) in contains()
109 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); in contains()

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