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Searched refs:RefI (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DBitTracker.h192 BitRef RefI; member
196 BitValue(unsigned Reg, uint16_t Pos) : Type(Ref), RefI(Reg, Pos) {} in BitValue()
201 if (Type == Ref && !(RefI == V.RefI))
231 if (Type == Ref && RefI == Self) // Bottom.meet(V) = Bottom (i.e. This) in meet()
243 RefI = V.RefI; // This may be irrelevant, but copy anyway. in meet()
248 RefI = Self; in meet()
274 if (V.RefI.Reg != 0) in ref()
275 return BitValue(V.RefI.Reg, V.RefI.Pos); in ref()
H A DBitTracker.cpp109 OS << printv(BV.RefI.Reg) << '[' << BV.RefI.Pos << ']'; in operator <<()
133 if (IsRef && SV.Type == BT::BitValue::Ref && V.RefI.Reg == SV.RefI.Reg) { in operator <<()
135 SeqRef = (V.RefI.Pos == SV.RefI.Pos+1); in operator <<()
136 ConstRef = (V.RefI.Pos == SV.RefI.Pos); in operator <<()
138 if (SeqRef && V.RefI.Pos == SV.RefI.Pos+(i-Start)) in operator <<()
140 if (ConstRef && V.RefI.Pos == SV.RefI.Pos) in operator <<()
153 OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-' in operator <<()
154 << SV.RefI.Pos+(Count-1) << ']'; in operator <<()
170 OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-' in operator <<()
171 << SV.RefI.Pos+(Count-1) << ']'; in operator <<()
[all …]
H A DHexagonBitSimplify.cpp347 if (RC1[B1+i].Type == BitTracker::BitValue::Ref && RC1[B1+i].RefI.Reg == 0) in isEqual()
350 if (RC2[B2+i].Type == BitTracker::BitValue::Ref && RC2[B2+i].RefI.Reg == 0) in isEqual()
1847 Register Reg = RC[I].RefI.Reg; in matchHalf()
1848 unsigned P = RC[I].RefI.Pos; // The RefI.Pos will be advanced by I-B. in matchHalf()
1867 if (RV.RefI.Reg != Reg) in matchHalf()
1869 if (RV.RefI.Pos != i+Pos) in matchHalf()
2246 unsigned SrcR = B0.RefI.Reg; in genBitSplit()
2248 unsigned Pos = B0.RefI.Pos; in genBitSplit()
2255 if (V.RefI.Reg != SrcR || V.RefI.Pos != Pos+i) in genBitSplit()
2274 if (S0.Type != BitTracker::BitValue::Ref || S0.RefI.Reg != SrcR) in genBitSplit()
[all …]
H A DHexagonGenInsert.cpp257 unsigned Ind1 = BaseOrd[V1.RefI.Reg], Ind2 = BaseOrd[V2.RefI.Reg]; in operator ()()
261 assert(V1.RefI.Pos != V2.RefI.Pos && "Bit values should be different"); in operator ()()
262 return V1.RefI.Pos < V2.RefI.Pos; in operator ()()
700 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg == VR) in findSelfReference()
710 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg != VR) in findNonSelfReference()