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Searched refs:Reductions (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Vectorize/
H A DLoopVectorizationLegality.h302 const ReductionList &getReductionVars() const { return Reductions; } in getReductionVars()
309 return Reductions.find(PN)->second; in getRecurrenceDescriptor()
351 bool isReductionVariable(PHINode *PN) const { return Reductions.count(PN); } in isReductionVariable()
601 ReductionList Reductions; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def75 /// Reductions.
H A DVVPInstrInfo.td186 // Reductions
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h607 Reductions = 0x02, enumerator
610 All = Reductions | Recurrences | Simple | Reverse
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopInterchange.cpp1025 SmallPtrSetImpl<PHINode *> &Reductions) { in areInnerLoopExitPHIsSupported() argument
1031 if (any_of(PHI.users(), [&Reductions, OuterL](User *U) { in areInnerLoopExitPHIsSupported()
1034 (!Reductions.count(PN) && OuterL->contains(PN->getParent())); in areInnerLoopExitPHIsSupported()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DLoopVectorizationLegality.cpp839 Reductions[Phi] = RedDes; in canVectorizeInstrs()
1655 if (Reductions.size() || FixedOrderRecurrences.size()) { in isVectorizableEarlyExitLoop()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def608 ///// Reductions {
H A DIntrinsics.td2324 // Reductions
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGOpenMPRuntime.h118 llvm::Value *Reductions = nullptr; member
H A DCGStmtOpenMP.cpp4945 Data.Reductions = CGM.getOpenMPRuntime().emitTaskReductionInit( in EmitOMPTaskBasedDirective()
5132 if (Data.Reductions) { in EmitOMPTaskBasedDirective()
5424 if (Data.Reductions) { in processInReduction()
H A DCGOpenMPRuntime.cpp4651 if (Data.Reductions) { in emitTaskLoopCall()
4652 CGF.EmitStoreOfScalar(Data.Reductions, RedLVal); in emitTaskLoopCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFiveP800.td106 // VEXQ1 handle Complex Slide, Permutation, Reductions, Divide instructions.
H A DRISCVSchedSiFiveP600.td341 // VEXQ1 handle Complex Slide, Permutation, Reductions, Divide instructions.
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp164 setEnableBit(TailFoldingOpts::Reductions); in operator =()
170 setDisableBit(TailFoldingOpts::Reductions); in operator =()
5878 Required |= TailFoldingOpts::Reductions; in preferPredicateOverEpilogue()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrSIMD.td981 // Reductions already return 0 or 1, so and 1, setne 0, and seteq 1