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Searched refs:Recip (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp990 Value *Recip = Builder.CreateUnaryIntrinsic(Intrinsic::amdgcn_rcp, Den); in optimizeWithRcp() local
991 return Builder.CreateFMul(Num, Recip); in optimizeWithRcp()
994 Value *Recip = emitRcpIEEE1ULP(Builder, Den, false); in optimizeWithRcp() local
995 return Builder.CreateFMul(Num, Recip); in optimizeWithRcp()
H A DSIISelLowering.cpp10493 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS); in lowerFastUnsafeFDIV() local
10494 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, Flags); in lowerFastUnsafeFDIV()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp645 SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
17344 APFloat Recip = APFloat::getOne(N1APF.getSemantics()); in visitFDIV() local
17345 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); in visitFDIV()
17348 if (((st == APFloat::opOK && !Recip.isDenormal()) || in visitFDIV()
17356 TLI.isFPImmLegal(Recip, VT, ForCodeSize))) in visitFDIV()
17358 DAG.getConstantFP(Recip, DL, VT)); in visitFDIV()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17066 APFloat Recip(0.0f); in PerformVMulVCTPCombine() local
17067 if (!CN || !CN->getValueAPF().getExactInverse(&Recip)) in PerformVMulVCTPCombine()
17072 if (Recip.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact) != in PerformVMulVCTPCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td2685 // Recip. square root estimate