Searched refs:RdHi (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 4320 bits<4> RdHi; 4323 let Inst{19-16} = RdHi; 4332 bits<4> RdHi; 4335 let Inst{19-16} = RdHi; 4402 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 4404 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", 4405 [(set GPR:$RdLo, GPR:$RdHi, 4410 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4412 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", 4413 [(set GPR:$RdLo, GPR:$RdHi, [all …]
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| H A D | ARMInstrThumb2.td | 687 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, 688 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>, 691 bits<4> RdHi; 699 let Inst{11-8} = RdHi; 704 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), 706 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 707 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 710 bits<4> RdHi; 718 let Inst{11-8} = RdHi; 3077 [(set rGPR:$RdLo, rGPR:$RdHi, [all …]
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| H A D | ARMInstrFormats.td | 1021 bits<4> RdHi; 1022 let Inst{19-16} = RdHi;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrAtomics.td | 517 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,@earlyclobber $scratch", 519 class cmp_swap_128 : Pseudo<(outs GPR64common:$RdLo, GPR64common:$RdHi,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 8548 MCRegister RdHi = Inst.getOperand(0).getReg(); in validateInstruction() local 8550 if(RdHi == RdLo) { in validateInstruction()
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