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Searched refs:Rd1 (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp668 uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5); in decodeXTHeadMemPair() local
672 if (!Check(S, DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder))) in decodeXTHeadMemPair()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp3756 MCRegister Rd1 = Inst.getOperand(0).getReg(); in validateInstruction() local
3760 if (Rs1 == Rd1 || Rs1 == Rd2 || Rd1 == Rd2) { in validateInstruction()
3767 MCRegister Rd1 = Inst.getOperand(0).getReg(); in validateInstruction() local
3769 if (Rd1 == Rd2) { in validateInstruction()