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Searched refs:Rd1 (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp457 uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5); in decodeXTHeadMemPair() local
461 DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder); in decodeXTHeadMemPair()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp3483 unsigned Rd1 = Inst.getOperand(0).getReg(); in validateInstruction() local
3487 if (Rs1 == Rd1 && Rs1 == Rd2) { in validateInstruction()
3494 unsigned Rd1 = Inst.getOperand(0).getReg(); in validateInstruction() local
3496 if (Rd1 == Rd2) { in validateInstruction()