Searched refs:Rb (Results 1 – 7 of 7) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCExpandPseudos.cpp | 91 Register Rb = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ() local 95 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(ARC::MOV_cc_ru6), Rb) in expandCTLZ() 103 .addReg(Rb); in expandCTLZ()
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/freebsd/crypto/openssl/crypto/ec/asm/ |
H A D | ecp_nistz256-x86_64.pl | 2558 my ($ONE,$INDEX,$Ra,$Rb,$Rc,$Rd,$Re,$Rf)=map("%xmm$_",(0..7)); 2622 pxor $Rb, $Rb 2650 por $T0b, $Rb 2663 movdqu $Rb, 16*1($val) 2742 pxor $Rb, $Rb 2764 por $T0b, $Rb 2774 movdqu $Rb, 16*1($val) 2800 my ($TWO,$INDEX,$Ra,$Rb,$Rc)=map("%ymm$_",(0..4)); 2834 vpxor $Rb, $Rb, $Rb 2869 vpxor $T0b, $Rb, $Rb [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonConstExtenders.cpp | 1049 OffsetRange HCE::getOffsetRange(Register Rb, const MachineInstr &MI) const { in getOffsetRange() argument 1058 if (Rb != Register(Op1) || !Op2.isImm()) in getOffsetRange() 1073 Rb != Register(MI.getOperand(BaseP)) || in getOffsetRange()
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H A D | HexagonPatterns.td | 955 def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), 956 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; 957 def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), 958 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>;
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/freebsd/contrib/flex/ |
H A D | NEWS | 479 ** Removed %option reentrant-bison/--reentrant-bison/-Rb 691 %option reentrant-bison (-Rb)
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H A D | ChangeLog | 5293 Removed %option reentrant-bison/--reentrant-bison/-Rb. Scanner
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrFormats.td | 2956 // add Rd, Rb, -imm -> sub Rd, Rn, imm
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