1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * Allwinner Gigabit Ethernet 28 */ 29 30 #ifndef __IF_AWGREG_H__ 31 #define __IF_AWGREG_H__ 32 33 #define EMAC_BASIC_CTL_0 0x00 34 #define BASIC_CTL_SPEED (0x3 << 2) 35 #define BASIC_CTL_SPEED_SHIFT 2 36 #define BASIC_CTL_SPEED_1000 0 37 #define BASIC_CTL_SPEED_10 2 38 #define BASIC_CTL_SPEED_100 3 39 #define BASIC_CTL_LOOPBACK (1 << 1) 40 #define BASIC_CTL_DUPLEX (1 << 0) 41 #define EMAC_BASIC_CTL_1 0x04 42 #define BASIC_CTL_BURST_LEN (0x3f << 24) 43 #define BASIC_CTL_BURST_LEN_SHIFT 24 44 #define BASIC_CTL_RX_TX_PRI (1 << 1) 45 #define BASIC_CTL_SOFT_RST (1 << 0) 46 #define EMAC_INT_STA 0x08 47 #define RX_BUF_UA_INT (1 << 10) 48 #define RX_INT (1 << 8) 49 #define TX_UNDERFLOW_INT (1 << 4) 50 #define TX_BUF_UA_INT (1 << 2) 51 #define TX_DMA_STOPPED_INT (1 << 1) 52 #define TX_INT (1 << 0) 53 #define EMAC_INT_EN 0x0c 54 #define RX_BUF_UA_INT_EN (1 << 10) 55 #define RX_INT_EN (1 << 8) 56 #define TX_UNDERFLOW_INT_EN (1 << 4) 57 #define TX_BUF_UA_INT_EN (1 << 2) 58 #define TX_DMA_STOPPED_INT_EN (1 << 1) 59 #define TX_INT_EN (1 << 0) 60 #define EMAC_TX_CTL_0 0x10 61 #define TX_EN (1 << 31) 62 #define EMAC_TX_CTL_1 0x14 63 #define TX_DMA_START (1 << 31) 64 #define TX_DMA_EN (1 << 30) 65 #define TX_NEXT_FRAME (1 << 2) 66 #define TX_MD (1 << 1) 67 #define FLUSH_TX_FIFO (1 << 0) 68 #define EMAC_TX_FLOW_CTL 0x1c 69 #define PAUSE_TIME (0xffff << 4) 70 #define PAUSE_TIME_SHIFT 4 71 #define TX_FLOW_CTL_EN (1 << 0) 72 #define EMAC_TX_DMA_LIST 0x20 73 #define EMAC_RX_CTL_0 0x24 74 #define RX_EN (1 << 31) 75 #define JUMBO_FRM_EN (1 << 29) 76 #define STRIP_FCS (1 << 28) 77 #define CHECK_CRC (1 << 27) 78 #define RX_FLOW_CTL_EN (1 << 16) 79 #define EMAC_RX_CTL_1 0x28 80 #define RX_DMA_START (1 << 31) 81 #define RX_DMA_EN (1 << 30) 82 #define RX_MD (1 << 1) 83 #define EMAC_RX_DMA_LIST 0x34 84 #define EMAC_RX_FRM_FLT 0x38 85 #define DIS_ADDR_FILTER (1 << 31) 86 #define DIS_BROADCAST (1 << 17) 87 #define RX_ALL_MULTICAST (1 << 16) 88 #define CTL_FRM_FILTER (0x3 << 12) 89 #define CTL_FRM_FILTER_SHIFT 12 90 #define HASH_MULTICAST (1 << 9) 91 #define HASH_UNICAST (1 << 8) 92 #define SA_FILTER_EN (1 << 6) 93 #define SA_INV_FILTER (1 << 5) 94 #define DA_INV_FILTER (1 << 4) 95 #define FLT_MD (1 << 1) 96 #define RX_ALL (1 << 0) 97 #define EMAC_RX_HASH_0 0x40 98 #define EMAC_RX_HASH_1 0x44 99 #define EMAC_MII_CMD 0x48 100 #define MDC_DIV_RATIO_M (0x7 << 20) 101 #define MDC_DIV_RATIO_M_16 0 102 #define MDC_DIV_RATIO_M_32 1 103 #define MDC_DIV_RATIO_M_64 2 104 #define MDC_DIV_RATIO_M_128 3 105 #define MDC_DIV_RATIO_M_SHIFT 20 106 #define PHY_ADDR (0x1f << 12) 107 #define PHY_ADDR_SHIFT 12 108 #define PHY_REG_ADDR (0x1f << 4) 109 #define PHY_REG_ADDR_SHIFT 4 110 #define MII_WR (1 << 1) 111 #define MII_BUSY (1 << 0) 112 #define EMAC_MII_DATA 0x4c 113 #define EMAC_ADDR_HIGH(n) (0x50 + (n) * 8) 114 #define EMAC_ADDR_LOW(n) (0x54 + (n) * 8) 115 #define EMAC_TX_DMA_STA 0xb0 116 #define EMAC_TX_DMA_CUR_DESC 0xb4 117 #define EMAC_TX_DMA_CUR_BUF 0xb8 118 #define EMAC_RX_DMA_STA 0xc0 119 #define EMAC_RX_DMA_CUR_DESC 0xc4 120 #define EMAC_RX_DMA_CUR_BUF 0xc8 121 #define EMAC_RGMII_STA 0xd0 122 123 struct emac_desc { 124 uint32_t status; 125 /* Transmit */ 126 #define TX_DESC_CTL (1 << 31) 127 #define TX_HEADER_ERR (1 << 16) 128 #define TX_LENGTH_ERR (1 << 14) 129 #define TX_PAYLOAD_ERR (1 << 12) 130 #define TX_CRS_ERR (1 << 10) 131 #define TX_COL_ERR_0 (1 << 9) 132 #define TX_COL_ERR_1 (1 << 8) 133 #define TX_COL_CNT (0xf << 3) 134 #define TX_COL_CNT_SHIFT 3 135 #define TX_DEFER_ERR (1 << 2) 136 #define TX_UNDERFLOW_ERR (1 << 1) 137 #define TX_DEFER (1 << 0) 138 /* Receive */ 139 #define RX_DESC_CTL (1 << 31) 140 #define RX_DAF_FAIL (1 << 30) 141 #define RX_FRM_LEN (0x3fff << 16) 142 #define RX_FRM_LEN_SHIFT 16 143 #define RX_NO_ENOUGH_BUF_ERR (1 << 14) 144 #define RX_SAF_FAIL (1 << 13) 145 #define RX_OVERFLOW_ERR (1 << 11) 146 #define RX_FIR_DESC (1 << 9) 147 #define RX_LAST_DESC (1 << 8) 148 #define RX_HEADER_ERR (1 << 7) 149 #define RX_COL_ERR (1 << 6) 150 #define RX_FRM_TYPE (1 << 5) 151 #define RX_LENGTH_ERR (1 << 4) 152 #define RX_PHY_ERR (1 << 3) 153 #define RX_CRC_ERR (1 << 1) 154 #define RX_PAYLOAD_ERR (1 << 0) 155 156 uint32_t size; 157 /* Transmit */ 158 #define TX_INT_CTL (1 << 31) 159 #define TX_LAST_DESC (1 << 30) 160 #define TX_FIR_DESC (1 << 29) 161 #define TX_CHECKSUM_CTL (0x3 << 27) 162 #define TX_CHECKSUM_CTL_IP 1 163 #define TX_CHECKSUM_CTL_NO_PSE 2 164 #define TX_CHECKSUM_CTL_FULL 3 165 #define TX_CHECKSUM_CTL_SHIFT 27 166 #define TX_CRC_CTL (1 << 26) 167 #define TX_BUF_SIZE (0xfff << 0) 168 #define TX_BUF_SIZE_SHIFT 0 169 /* Receive */ 170 #define RX_INT_CTL (1 << 31) 171 #define RX_BUF_SIZE (0xfff << 0) 172 #define RX_BUF_SIZE_SHIFT 0 173 174 uint32_t addr; 175 176 uint32_t next; 177 } __packed; 178 179 #endif /* !__IF_AWGREG_H__ */ 180