| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/ |
| H A D | RISCVCustomBehaviour.cpp | 300 if (const auto *RVV = in getSchedClassID() local
302 VPOpcode = RVV->Pseudo; in getSchedClassID()
305 const auto *RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW); in getSchedClassID() local
307 if (!RVV) in getSchedClassID()
308 RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0); in getSchedClassID()
310 if (RVV) in getSchedClassID()
311 VPOpcode = RVV->Pseudo; in getSchedClassID()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVVLOptimizer.cpp | 199 const RISCVVPseudosTable::PseudoInfo *RVV = in getOperandLog2EEW() local
201 assert(RVV && "Could not find MI in PseudoTable"); in getOperandLog2EEW()
220 switch (RVV->BaseInstr) { in getOperandLog2EEW()
758 const RISCVVPseudosTable::PseudoInfo *RVV = in getOperandInfo() local
760 assert(RVV && "Could not find MI in PseudoTable"); in getOperandInfo()
766 switch (RVV->BaseInstr) { in getOperandInfo()
798 const RISCVVPseudosTable::PseudoInfo *RVV = in isSupportedInstr() local
801 if (!RVV) in isSupportedInstr()
804 switch (RVV->BaseInstr) { in isSupportedInstr()
1174 const RISCVVPseudosTable::PseudoInfo *RVV = in isVectorOpUsedAsScalarOp() local
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| H A D | RISCVAsmPrinter.cpp | 1071 const RISCVVPseudosTable::PseudoInfo *RVV = in lowerRISCVVMachineInstrToMCInst() local
1073 if (!RVV) in lowerRISCVVMachineInstrToMCInst()
1076 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst()
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| H A D | RISCVInstrInfoVVLPatterns.td | 1 //===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===//
15 /// Note: the patterns for RVV intrinsics are found in
537 // Truncates a RVV integer vector by one power-of-two. Carries both an extra
542 // Truncates a RVV integer vector by one power-of-two. If the value doesn't
709 // These nodes match the semantics of the corresponding RVV vector reduction
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| H A D | RISCVInstrInfo.cpp | 4789 const RISCVVPseudosTable::PseudoInfo *RVV = in getRVVMCOpcode() local
4791 if (!RVV) in getRVVMCOpcode()
4793 return RVV->BaseInstr; in getRVVMCOpcode()
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| H A D | RISCVInstrInfoVSDPatterns.td | 1 //===- RISCVInstrInfoVSDPatterns.td - RVV SDNode patterns --*- tablegen -*-===//
15 /// Note: the patterns for RVV intrinsics are found in
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| /freebsd/contrib/llvm-project/clang/include/clang/Sema/ |
| H A D | RISCVIntrinsicManager.h | 27 enum class IntrinsicKind : uint8_t { RVV, SIFIVE_VECTOR, ANDES_VECTOR }; enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | VFABIDemangler.cpp | 46 .Case("r", VFISAKind::RVV) in tryParseISA()
84 if (ISA != VFISAKind::SVE && ISA != VFISAKind::RVV) { in tryParseVLEN()
306 assert((ISA == VFISAKind::SVE || ISA == VFISAKind::RVV) && in getElementCountForTy()
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| /freebsd/contrib/llvm-project/clang/lib/Basic/Targets/ |
| H A D | RISCV.cpp | 278 namespace RVV { namespace
331 {&RVV::BuiltinStrings, RVV::BuiltinInfos, "__builtin_rvv_"}, in getTargetBuiltins()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VFABIDemangler.h | 48 RVV, // RISC-V Vector Extension enumerator
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | riscv_vector_common.td | 9 // This file defines RVV builtin base class for RISC-V V-extension.
73 // will yield an RVV vector type (assume LMUL=1), so __rvv_int32m1_t.
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| H A D | DiagnosticSemaKinds.td | 3351 "invalid RVV vector size '%0', expected size is '%1' based on LMUL of type "
3354 "%0 attribute applied to non-RVV type %1">;
3500 "cannot combine fixed-length and sizeless %select{SVE|RVV}0 vectors "
3503 …"cannot combine GNU and %select{SVE|RVV}0 vectors in expression, result is ambiguous (%1 and %2)">;
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| H A D | AttrDocs.td | 2963 The attribute can be attached to a single RVV vector (such as ``vint8m1_t``).
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaRISCV.cpp | 103 case IntrinsicKind::RVV: in ProtoSeq2ArrayRef()
342 ConstructRVVIntrinsics(RVVIntrinsicRecords, IntrinsicKind::RVV); in InitIntrinsicList()
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| /freebsd/contrib/llvm-project/clang/include/clang/Driver/ |
| H A D | Options.td | 5132 HelpText<"Specify the size in bits of an RVV vector register">,
5134 "Specify the size in bits of an RVV vector register. Defaults to the "
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