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Searched refs:RSQ (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp309 Register RSQ = B.buildIntrinsic(Intrinsic::amdgcn_rsq, {DstTy}) in applyFDivSqrtToRsqF16() local
313 B.buildFMul(Dst, RSQ, Y, Flags); in applyFDivSqrtToRsqF16()
H A DAMDGPUISelLowering.h485 RSQ, enumerator
H A DAMDGPUInstrInfo.td130 def AMDGPUrsq_impl : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
H A DSIISelLowering.cpp8449 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
8466 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
11036 SDValue SqrtR = DAG.getNode(AMDGPUISD::RSQ, DL, VT, SqrtX, Flags); in lowerFSQRTF32()
11105 SDValue SqrtY = DAG.getNode(AMDGPUISD::RSQ, DL, MVT::f64, SqrtX); in lowerFSQRTF64()
12590 return DCI.DAG.getNode(AMDGPUISD::RSQ, SDLoc(N), VT, in performRcpCombine()
12642 case AMDGPUISD::RSQ: in isCanonicalized()
14419 DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0), Flags); in performFDivCombine()
14736 case AMDGPUISD::RSQ: in PerformDAGCombine()
H A DR600ISelLowering.cpp564 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerOperation()
H A DAMDGPUISelLowering.cpp5462 NODE_NAME_CASE(RSQ) in getTargetNodeName()
5586 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand); in getSqrtEstimate()
5933 case AMDGPUISD::RSQ: in isKnownNeverNaNForTargetNode()
H A DAMDGPUISelDAGToDAG.cpp178 case AMDGPUISD::RSQ: in fp16SrcZerosHighBits()
/freebsd/contrib/one-true-awk/testdir/
H A Dfunstack.in2782 note = "See also \cite{Hill:1981:RSQ}.",
27089 @Article{Hill:1981:RSQ,