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Searched refs:ROTL (Results 1 – 25 of 48) sorted by relevance

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/freebsd/contrib/bearssl/src/hash/
H A Dsha1.c32 #define ROTL(x, n) (((x) << (n)) | ((x) >> (32 - (n)))) macro
60 m[i] = ROTL(x, 1); in br_sha1_round()
64 e += ROTL(a, 5) + F(b, c, d) + K1 + m[i + 0]; b = ROTL(b, 30); in br_sha1_round()
65 d += ROTL(e, 5) + F(a, b, c) + K1 + m[i + 1]; a = ROTL(a, 30); in br_sha1_round()
66 c += ROTL(d, 5) + F(e, a, b) + K1 + m[i + 2]; e = ROTL(e, 30); in br_sha1_round()
67 b += ROTL(c, 5) + F(d, e, a) + K1 + m[i + 3]; d = ROTL(d, 30); in br_sha1_round()
68 a += ROTL(b, 5) + F(c, d, e) + K1 + m[i + 4]; c = ROTL(c, 30); in br_sha1_round()
71 e += ROTL(a, 5) + G(b, c, d) + K2 + m[i + 0]; b = ROTL(b, 30); in br_sha1_round()
72 d += ROTL(e, 5) + G(a, b, c) + K2 + m[i + 1]; a = ROTL(a, 30); in br_sha1_round()
73 c += ROTL(d, 5) + G(e, a, b) + K2 + m[i + 2]; e = ROTL(e, 30); in br_sha1_round()
[all …]
H A Dmd5.c32 #define ROTL(x, n) (((x) << (n)) | ((x) >> (32 - (n)))) macro
87 a = b + ROTL(a + F(b, c, d) + m[i + 0] + K[i + 0], 7); in br_md5_round()
88 d = a + ROTL(d + F(a, b, c) + m[i + 1] + K[i + 1], 12); in br_md5_round()
89 c = d + ROTL(c + F(d, a, b) + m[i + 2] + K[i + 2], 17); in br_md5_round()
90 b = c + ROTL(b + F(c, d, a) + m[i + 3] + K[i + 3], 22); in br_md5_round()
93 a = b + ROTL(a + G(b, c, d) + m[MP[i - 16]] + K[i + 0], 5); in br_md5_round()
94 d = a + ROTL(d + G(a, b, c) + m[MP[i - 15]] + K[i + 1], 9); in br_md5_round()
95 c = d + ROTL(c + G(d, a, b) + m[MP[i - 14]] + K[i + 2], 14); in br_md5_round()
96 b = c + ROTL(b + G(c, d, a) + m[MP[i - 13]] + K[i + 3], 20); in br_md5_round()
99 a = b + ROTL(a + H(b, c, d) + m[MP[i - 16]] + K[i + 0], 4); in br_md5_round()
[all …]
/freebsd/contrib/unbound/util/
H A Dsiphash.c38 #define ROTL(x, b) (uint64_t)(((x) << (b)) | ((x) >> (64 - (b)))) macro
59 v1 = ROTL(v1, 13); \
61 v0 = ROTL(v0, 32); \
63 v3 = ROTL(v3, 16); \
66 v3 = ROTL(v3, 21); \
69 v1 = ROTL(v1, 17); \
71 v2 = ROTL(v2, 32); \
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DSipHash.cpp32 #define ROTL(x, b) (uint64_t)(((x) << (b)) | ((x) >> (64 - (b)))) macro
37 v1 = ROTL(v1, 13); \
39 v0 = ROTL(v0, 32); \
41 v3 = ROTL(v3, 16); \
44 v3 = ROTL(v3, 21); \
47 v1 = ROTL(v1, 17); \
49 v2 = ROTL(v2, 32); \
/freebsd/crypto/openssl/crypto/siphash/
H A Dsiphash.c32 #define ROTL(x, b) (uint64_t)(((x) << (b)) | ((x) >> (64 - (b)))) macro
53 v1 = ROTL(v1, 13); \
55 v0 = ROTL(v0, 32); \
57 v3 = ROTL(v3, 16); \
60 v3 = ROTL(v3, 21); \
63 v1 = ROTL(v1, 17); \
65 v2 = ROTL(v2, 32); \
/freebsd/crypto/openssl/crypto/cast/
H A Dcast_local.h117 # define ROTL(a,n) (_lrotl(a,n)) macro
119 # define ROTL(a,n) ((((a)<<(n))&0xffffffffL)|((a)>>((32-(n))&31))) macro
135 t=ROTL(t,i); \
152 w=ROTL(w,i); \
172 t=ROTL(t,(key[n*2+1])); \
/freebsd/crypto/openssl/crypto/bn/asm/
H A Dppc.pl132 $ROTL= "rotlwi"; # rotate left by immediate
156 $ROTL= "rotldi"; # rotate left by immediate
1727 $ROTL r3,r11,`$BITS/2` # rotate by $BITS/2 and store in r3
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3482 { ISD::ROTL, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3483 { ISD::ROTL, MVT::v16i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3484 { ISD::ROTL, MVT::v8i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3575 { ISD::ROTL, MVT::v32i16, { 2, 8, 6, 8 } }, in getIntrinsicInstrCost()
3576 { ISD::ROTL, MVT::v16i16, { 2, 8, 6, 7 } }, in getIntrinsicInstrCost()
3577 { ISD::ROTL, MVT::v8i16, { 2, 7, 6, 7 } }, in getIntrinsicInstrCost()
3578 { ISD::ROTL, MVT::v64i8, { 5, 6, 11, 12 } }, in getIntrinsicInstrCost()
3579 { ISD::ROTL, MVT::v32i8, { 5, 15, 7, 10 } }, in getIntrinsicInstrCost()
3580 { ISD::ROTL, MVT::v16i8, { 5, 15, 7, 10 } }, in getIntrinsicInstrCost()
3639 { ISD::ROTL, MVT::v8i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
[all …]
H A DX86InstrShiftRotate.td530 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
535 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h736 ROTL, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp98 setOperationAction(ISD::ROTL, MVT::i8, Custom); in AVRTargetLowering()
99 setOperationAction(ISD::ROTL, MVT::i16, Expand); in AVRTargetLowering()
333 case ISD::ROTL: { in LowerShifts()
360 case ISD::ROTL: in LowerShifts()
413 } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 3) { in LowerShifts()
425 } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 7) { in LowerShifts()
435 } else if ((Op.getOpcode() == ISD::ROTR || Op.getOpcode() == ISD::ROTL) && in LowerShifts()
985 case ISD::ROTL: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td69 defm ROTL : BinaryInt<rotl, "rotl", 0x77, 0x89>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1601 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1650 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1829 setOperationAction(ISD::ROTL, MVT::i32, Legal); in HexagonTargetLowering()
1830 setOperationAction(ISD::ROTL, MVT::i64, Legal); in HexagonTargetLowering()
3381 case ISD::ROTL: return LowerROTL(Op, DAG); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp81 setOperationAction(ISD::ROTL, MVT::i8, Expand); in MSP430TargetLowering()
83 setOperationAction(ISD::ROTL, MVT::i16, Expand); in MSP430TargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp860 case ISD::ROTL: { in expandRxSBG()
1639 case ISD::ROTL: in Select()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp281 case ISD::ROTL: return "rotl"; in getOperationName()
H A DLegalizeVectorOps.cpp367 case ISD::ROTL: in LegalizeOp()
1001 case ISD::ROTL: in Expand()
H A DLegalizeIntegerTypes.cpp310 case ISD::ROTL: in PromoteIntegerResult()
1976 case ISD::ROTL: in PromoteIntegerOperand()
2934 case ISD::ROTL: in ExpandIntegerResult()
5184 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
5282 case ISD::ROTL: in ExpandIntegerOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp111 setOperationAction(ISD::ROTL, VT, Expand); in BPFTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp533 ISD::ROTL, ISD::ROTR, ISD::SADDO, ISD::SADDO_CARRY, in NVPTXTargetLowering()
576 setOperationAction(ISD::ROTL, MVT::i64, Legal); in NVPTXTargetLowering()
578 setOperationAction(ISD::ROTL, MVT::i32, Legal); in NVPTXTargetLowering()
581 setOperationAction(ISD::ROTL, MVT::i16, Expand); in NVPTXTargetLowering()
582 setOperationAction(ISD::ROTL, MVT::v2i16, Expand); in NVPTXTargetLowering()
585 setOperationAction(ISD::ROTL, MVT::i8, Expand); in NVPTXTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp81 setOperationAction(ISD::ROTL, GRLenVT, Expand); in LoongArchTargetLowering()
132 setOperationAction(ISD::ROTL, MVT::i32, Custom); in LoongArchTargetLowering()
2632 case ISD::ROTL: in getLoongArchWOpcode()
2664 if (N->getOpcode() == ISD::ROTL) { in customLegalizeToWOp()
2836 case ISD::ROTL: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp682 } else if (Opcode == ISD::ROTL) { in isRotateAndMask()
1623 case ISD::ROTL: in getValueBits()
4103 case ISD::ROTL: in tryBitPermutation()
4964 if (isRunOfOnes(Imm, MB, ME) && Val.getOpcode() != ISD::ROTL) { in tryAsSingleRLWINM()
5107 if (Val.getOpcode() != ISD::ROTL) in tryAsSingleRLDCL()
H A DPPCISelLowering.cpp883 setOperationAction(ISD::ROTL, VT, Expand); in PPCTargetLowering()
934 setOperationAction(ISD::ROTL, MVT::v1i128, Custom); in PPCTargetLowering()
938 setOperationAction(ISD::ROTL, VT, Legal); in PPCTargetLowering()
941 setOperationAction(ISD::ROTL, MVT::v2i64, Legal); in PPCTargetLowering()
980 setOperationAction(ISD::ROTL, MVT::v1i128, Legal); in PPCTargetLowering()
10117 assert(Op.getOpcode() == ISD::ROTL && "Should only be called for ISD::ROTL"); in LowerROTL()
10880 return DAG.getNode(ISD::ROTL, dl, MVT::i64, Src, Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN()
10887 Src = DAG.getNode(ISD::ROTL, dl, MVT::i64, Src, in LowerINTRINSIC_WO_CHAIN()
10890 Src = DAG.getNode(ISD::ROTL, dl, MVT::i64, Src, in LowerINTRINSIC_WO_CHAIN()
10906 return DAG.getNode(ISD::ROTL, dl, MVT::i32, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp120 setOperationAction(ISD::ROTL, MVT::i32, Expand); in LanaiTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp341 setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom); in RISCVTargetLowering()
344 setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom); in RISCVTargetLowering()
345 setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Custom); in RISCVTargetLowering()
347 setOperationAction(ISD::ROTL, XLenVT, Expand); in RISCVTargetLowering()
349 setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand); in RISCVTargetLowering()
351 setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Expand); in RISCVTargetLowering()
904 setOperationAction({ISD::ROTL, ISD::ROTR}, VT, Expand); in RISCVTargetLowering()
1268 setOperationAction({ISD::BSWAP, ISD::ROTL, ISD::ROTR}, VT, Custom); in RISCVTargetLowering()
4987 Rotate = DAG.getNode(ISD::ROTL, DL, RotateVT, Op, in lowerVECTOR_SHUFFLEAsRotate()
5968 OP_CASE(ROTL) in getRISCVVLOp()
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