Home
last modified time | relevance | path

Searched refs:ROR (Results 1 – 25 of 44) sorted by relevance

12

/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha512-ppc.pl87 $ROR="rotrdi";
99 $ROR="rotrwi";
137 $ROR $a0,$e,$Sigma1[0]
138 $ROR $a1,$e,$Sigma1[1]
143 $ROR $a1,$a1,`$Sigma1[2]-$Sigma1[1]`
150 $ROR $a0,$a,$Sigma0[0]
151 $ROR $a1,$a,$Sigma0[1]
155 $ROR $a1,$a1,`$Sigma0[2]-$Sigma0[1]`
176 $ROR $a0,@X[($i+1)%16],$sigma0[0]
177 $ROR $a1,@X[($i+1)%16],$sigma0[1]
[all …]
/freebsd/sys/crypto/openssl/arm/
H A Dsha1-armv4-large.S53 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
59 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
78 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
84 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
103 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
109 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
128 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
134 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
153 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
159 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td16 /// ROL [~] ROR [~] ROXL [ ] ROXR [ ]
98 defm ROR : MxSROp<"ror", rotr, MxRODI_R, MxROOP_RO>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h37 ROR, enumerator
58 case AArch64_AM::ROR: return "ror"; in getShiftExtendName()
79 case 3: return AArch64_AM::ROR; in getShiftType()
107 case AArch64_AM::ROR: STEnc = 3; break; in getShifterImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredicates.td57 def CheckShiftROR : CheckImmOperand_s<3, "AArch64_AM::ROR">;
342 // Identify EXTR as the alias for ROR (immediate).
H A DAArch64SchedNeoverseV1.td609 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
616 // Arithmetic, flagset, LSR/ASR/ROR shift or LSL shift > 4
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h182 static inline uint32_t ROR(const uint32_t value, const uint32_t amount, in ROR() function
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVOptWInstrs.cpp270 case RISCV::ROR: in hasAllNBitUsers()
H A DRISCVInstrInfoZb.td305 def ROR : ALU_rr<0b0110000, 0b101, "ror">,
510 def : PatGprGpr<shiftop<rotr>, ROR>;
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1755 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRRtPCRelative()
6340 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRImmediateARM()
6445 data = ROR(data, Bits32(address, 1, 0), &success); in EmulateLDRImmediateARM()
6478 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRRegister()
6650 data = ROR(data, Bits32(address, 1, 0), &success); in EmulateLDRRegister()
8326 rotated = ROR(R[m], rotation); in EmulateSXTB()
8381 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateSXTB()
8411 rotated = ROR(R[m], rotation); in EmulateSXTH()
8466 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateSXTH()
8496 rotated = ROR(R[m], rotation); in EmulateUXTB()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h695 ROR, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp312 Opc8 = AVRISD::ROR; in LowerShifts()
363 Victim = DAG.getNode(AVRISD::ROR, dl, VT, Victim); in LowerShifts()
372 Victim = DAG.getNode(AVRISD::ROR, dl, VT, Victim); in LowerShifts()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedSandyBridge.td1000 "ROR(8|16|32|64)m(1|i)")>;
1038 "ROR(8|16|32|64)mCL",
H A DX86ScheduleZnver4.td1586 "(V?)P(ROL|ROR)(D|Q|VD|VQ)(Z?|Z128?|Z256?)(rr|rrk|rrkz)",
1587 "(V?)P(ROL|ROR)(D|Q|VD|VQ)(Z256?)(ri|rik|rikz)",
1588 "(V?)P(ROL|ROR)(D|Q)(Z?|Z128?)(ri|rik|rikz)",
H A DX86SchedSkylakeClient.td1135 "ROR(8|16|32|64)m(1|i)")>;
1218 "ROR(8|16|32|64)mCL",
H A DX86SchedBroadwell.td1081 "ROR(8|16|32|64)m(1|i)")>;
1155 "ROR(8|16|32|64)mCL",
H A DX86SchedHaswell.td1185 "ROR(8|16|32|64)m(1|i)")>;
1316 "ROR(8|16|32|64)mCL",
H A DX86ScheduleAtom.td514 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
H A DX86SchedSkylakeServer.td1429 "ROR(8|16|32|64)m(1|i)")>;
1601 "ROR(8|16|32|64)mCL",
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM7.td338 def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)r", "tROR")>;
H A DARMScheduleSwift.td154 // ASR,LSL,ROR,RRX
H A DARMScheduleM85.td439 (instregex "(t|t2)(LSL|LSR|ASR|ROR|SBFX|UBFX)")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.td304 defm ROR : ArcBinaryEXT5Inst<0b000011, "ror">;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1521 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR || in isShifter()
1634 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) && in isLogicalShifter()
3658 .Case("ror", AArch64_AM::ROR) in tryParseOptionalShiftExtend()
3680 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
/freebsd/sys/dev/axgbe/
H A Dxgbe-dev.c2458 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); in xgbe_config_mmc()

12