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Searched refs:ROL (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td16 /// ROL [~] ROR [~] ROXL [ ] ROXR [ ]
97 defm ROL : MxSROp<"rol", rotl, MxRODI_L, MxROOP_RO>;
/freebsd/sys/opencrypto/
H A Drmd160.c72 #define ROL(n, x) (((x) << (n)) | ((x) >> (32-(n)))) macro
82 a = ROL(sj, a + Fj(b,c,d) + X(rj) + Kj) + e; \
83 c = ROL(10, c); \
/freebsd/contrib/diff/src/
H A Dio.c30 #define ROL(v, n) ((v) << (n) | (v) >> (sizeof (v) * CHAR_BIT - (n))) macro
33 #define HASH(h, c) ((c) + ROL (h, 7))
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.h54 ROL, ///< Bit rotate left. enumerator
H A DAVRISelLowering.cpp240 NODE(ROL); in getTargetNodeName()
361 Opc8 = AVRISD::ROL; in LowerShifts()
423 DAG.getNode(AVRISD::ROL, dl, VT, Victim, DAG.getConstant(1, dl, VT)); in LowerShifts()
433 DAG.getNode(AVRISD::ROL, dl, VT, Victim, DAG.getConstant(1, dl, VT)); in LowerShifts()
H A DAVRInstrInfo.td60 def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>;
1647 def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8 : $rd, GPR8 : $rd)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVOptWInstrs.cpp253 case RISCV::ROL: in hasAllNBitUsers()
H A DRISCVInstrInfoZb.td307 def ROL : ALU_rr<0b0110000, 0b001, "rol">,
503 def : PatGprGpr<shiftop<rotl>, ROL>;
H A DRISCVISelDAGToDAG.cpp3166 case RISCV::ROL: in hasAllNBitUsers()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedSandyBridge.td992 def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)",
1030 def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL",
H A DX86ScheduleZnver4.td1585 "(V?)P(ROL|ROR)(D|Q|VD|VQ)(Z?|Z128?|Z256?)(rr|rrk|rrkz)",
1586 "(V?)P(ROL|ROR)(D|Q|VD|VQ)(Z256?)(ri|rik|rikz)",
1587 "(V?)P(ROL|ROR)(D|Q)(Z?|Z128?)(ri|rik|rikz)",
H A DX86SchedBroadwell.td1090 def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
1164 def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
H A DX86SchedSkylakeClient.td1146 def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
1229 def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
H A DX86SchedHaswell.td1192 def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)",
1323 def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL",
H A DX86ScheduleAtom.td514 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
H A DX86InstrCompiler.td1887 // ROL/ROR instructions allow a stronger mask optimization than shift for 8- and
1937 defm ROL : MaskedRotateAmountPats<rotl>;
2203 // register-register 16 bit bswap. This maps it to a ROL instruction.
H A DX86SchedSkylakeServer.td1443 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
1616 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
H A DX86SchedIceLake.td1454 def: InstRW<[ICXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
1631 def: InstRW<[ICXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2639 case Mips::ROL: in tryExpandInstruction()
4945 if (Inst.getOpcode() == Mips::ROL) { in expandRotation()
4963 case Mips::ROL: in expandRotation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.td2530 def ROL : MipsAsmPseudoInst<(outs),
2537 (ROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
/freebsd/contrib/diff/
H A DChangeLog2082 * io.c (ROL): Use sizeof to make it more generic.
/freebsd/share/ctypedef/
H A DC.UTF-8.src32424 <LEPCHA_PUNCTUATION_TA-ROL>;/
32425 <LEPCHA_PUNCTUATION_NYET_THYOOM_TA-ROL>;/
/freebsd/share/misc/
H A Dpci_vendors23187 8139 ROL/F-100 Fast Ethernet Adapter with ROL
/freebsd/tools/tools/locale/etc/final-maps/
H A Dmap.GB180305808 <LEPCHA_PUNCTUATION_TA-ROL> \x81\x35\xC1\…
5809 <LEPCHA_PUNCTUATION_NYET_THYOOM_TA-ROL> \x81\x35\xC1\…
/freebsd/share/colldef/
H A Dzh_CN.GB18030.src56145 …UNCTUATION_TA-ROL> "<X0924><X1000>";<X05…
56146 …YET_THYOOM_TA-ROL> "<X0924><X1700>";<X05>;"<X05><XC0…

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