1 /* 2 * Copyright (c) 2018-2019 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef __QLNXR_ROCE_H__ 30 #define __QLNXR_ROCE_H__ 31 32 /* 33 * roce completion notification queue element 34 */ 35 struct roce_cnqe { 36 struct regpair cq_handle; 37 }; 38 39 struct roce_cqe_responder { 40 struct regpair srq_wr_id; 41 struct regpair qp_handle; 42 __le32 imm_data_or_inv_r_Key; 43 __le32 length; 44 __le32 reserved0; 45 __le16 rq_cons; 46 u8 flags; 47 #define ROCE_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1 48 #define ROCE_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0 49 #define ROCE_CQE_RESPONDER_TYPE_MASK 0x3 50 #define ROCE_CQE_RESPONDER_TYPE_SHIFT 1 51 #define ROCE_CQE_RESPONDER_INV_FLG_MASK 0x1 52 #define ROCE_CQE_RESPONDER_INV_FLG_SHIFT 3 53 #define ROCE_CQE_RESPONDER_IMM_FLG_MASK 0x1 54 #define ROCE_CQE_RESPONDER_IMM_FLG_SHIFT 4 55 #define ROCE_CQE_RESPONDER_RDMA_FLG_MASK 0x1 56 #define ROCE_CQE_RESPONDER_RDMA_FLG_SHIFT 5 57 #define ROCE_CQE_RESPONDER_RESERVED2_MASK 0x3 58 #define ROCE_CQE_RESPONDER_RESERVED2_SHIFT 6 59 u8 status; 60 }; 61 62 struct roce_cqe_requester { 63 __le16 sq_cons; 64 __le16 reserved0; 65 __le32 reserved1; 66 struct regpair qp_handle; 67 struct regpair reserved2; 68 __le32 reserved3; 69 __le16 reserved4; 70 u8 flags; 71 #define ROCE_CQE_REQUESTER_TOGGLE_BIT_MASK 0x1 72 #define ROCE_CQE_REQUESTER_TOGGLE_BIT_SHIFT 0 73 #define ROCE_CQE_REQUESTER_TYPE_MASK 0x3 74 #define ROCE_CQE_REQUESTER_TYPE_SHIFT 1 75 #define ROCE_CQE_REQUESTER_RESERVED5_MASK 0x1F 76 #define ROCE_CQE_REQUESTER_RESERVED5_SHIFT 3 77 u8 status; 78 }; 79 80 struct roce_cqe_common { 81 struct regpair reserved0; 82 struct regpair qp_handle; 83 __le16 reserved1[7]; 84 u8 flags; 85 #define ROCE_CQE_COMMON_TOGGLE_BIT_MASK 0x1 86 #define ROCE_CQE_COMMON_TOGGLE_BIT_SHIFT 0 87 #define ROCE_CQE_COMMON_TYPE_MASK 0x3 88 #define ROCE_CQE_COMMON_TYPE_SHIFT 1 89 #define ROCE_CQE_COMMON_RESERVED2_MASK 0x1F 90 #define ROCE_CQE_COMMON_RESERVED2_SHIFT 3 91 u8 status; 92 }; 93 94 /* 95 * roce completion queue element 96 */ 97 union roce_cqe { 98 struct roce_cqe_responder resp; 99 struct roce_cqe_requester req; 100 struct roce_cqe_common cmn; 101 }; 102 103 /* 104 * CQE requester status enumeration 105 */ 106 enum roce_cqe_requester_status_enum { 107 ROCE_CQE_REQ_STS_OK, 108 ROCE_CQE_REQ_STS_BAD_RESPONSE_ERR, 109 ROCE_CQE_REQ_STS_LOCAL_LENGTH_ERR, 110 ROCE_CQE_REQ_STS_LOCAL_QP_OPERATION_ERR, 111 ROCE_CQE_REQ_STS_LOCAL_PROTECTION_ERR, 112 ROCE_CQE_REQ_STS_MEMORY_MGT_OPERATION_ERR, 113 ROCE_CQE_REQ_STS_REMOTE_INVALID_REQUEST_ERR, 114 ROCE_CQE_REQ_STS_REMOTE_ACCESS_ERR, 115 ROCE_CQE_REQ_STS_REMOTE_OPERATION_ERR, 116 ROCE_CQE_REQ_STS_RNR_NAK_RETRY_CNT_ERR, 117 ROCE_CQE_REQ_STS_TRANSPORT_RETRY_CNT_ERR, 118 ROCE_CQE_REQ_STS_WORK_REQUEST_FLUSHED_ERR, 119 MAX_ROCE_CQE_REQUESTER_STATUS_ENUM 120 }; 121 122 /* 123 * CQE responder status enumeration 124 */ 125 enum roce_cqe_responder_status_enum { 126 ROCE_CQE_RESP_STS_OK, 127 ROCE_CQE_RESP_STS_LOCAL_ACCESS_ERR, 128 ROCE_CQE_RESP_STS_LOCAL_LENGTH_ERR, 129 ROCE_CQE_RESP_STS_LOCAL_QP_OPERATION_ERR, 130 ROCE_CQE_RESP_STS_LOCAL_PROTECTION_ERR, 131 ROCE_CQE_RESP_STS_MEMORY_MGT_OPERATION_ERR, 132 ROCE_CQE_RESP_STS_REMOTE_INVALID_REQUEST_ERR, 133 ROCE_CQE_RESP_STS_WORK_REQUEST_FLUSHED_ERR, 134 MAX_ROCE_CQE_RESPONDER_STATUS_ENUM 135 }; 136 137 /* 138 * CQE type enumeration 139 */ 140 enum roce_cqe_type { 141 ROCE_CQE_TYPE_REQUESTER, 142 ROCE_CQE_TYPE_RESPONDER_RQ, 143 ROCE_CQE_TYPE_RESPONDER_SRQ, 144 ROCE_CQE_TYPE_INVALID, 145 MAX_ROCE_CQE_TYPE 146 }; 147 148 /* 149 * memory window type enumeration 150 */ 151 enum roce_mw_type { 152 ROCE_MW_TYPE_1, 153 ROCE_MW_TYPE_2A, 154 MAX_ROCE_MW_TYPE 155 }; 156 157 struct roce_rq_sge { 158 struct regpair addr; 159 __le32 length; 160 __le32 flags; 161 #define ROCE_RQ_SGE_L_KEY_MASK 0x3FFFFFF 162 #define ROCE_RQ_SGE_L_KEY_SHIFT 0 163 #define ROCE_RQ_SGE_NUM_SGES_MASK 0x7 164 #define ROCE_RQ_SGE_NUM_SGES_SHIFT 26 165 #define ROCE_RQ_SGE_RESERVED0_MASK 0x7 166 #define ROCE_RQ_SGE_RESERVED0_SHIFT 29 167 }; 168 169 struct roce_sq_atomic_wqe { 170 struct regpair remote_va; 171 __le32 xrc_srq; 172 u8 req_type; 173 u8 flags; 174 #define ROCE_SQ_ATOMIC_WQE_COMP_FLG_MASK 0x1 175 #define ROCE_SQ_ATOMIC_WQE_COMP_FLG_SHIFT 0 176 #define ROCE_SQ_ATOMIC_WQE_RD_FENCE_FLG_MASK 0x1 177 #define ROCE_SQ_ATOMIC_WQE_RD_FENCE_FLG_SHIFT 1 178 #define ROCE_SQ_ATOMIC_WQE_INV_FENCE_FLG_MASK 0x1 179 #define ROCE_SQ_ATOMIC_WQE_INV_FENCE_FLG_SHIFT 2 180 #define ROCE_SQ_ATOMIC_WQE_SE_FLG_MASK 0x1 181 #define ROCE_SQ_ATOMIC_WQE_SE_FLG_SHIFT 3 182 #define ROCE_SQ_ATOMIC_WQE_INLINE_FLG_MASK 0x1 183 #define ROCE_SQ_ATOMIC_WQE_INLINE_FLG_SHIFT 4 184 #define ROCE_SQ_ATOMIC_WQE_RESERVED0_MASK 0x7 185 #define ROCE_SQ_ATOMIC_WQE_RESERVED0_SHIFT 5 186 u8 reserved1; 187 u8 prev_wqe_size; 188 struct regpair swap_data; 189 __le32 r_key; 190 __le32 reserved2; 191 struct regpair cmp_data; 192 struct regpair reserved3; 193 }; 194 195 /* 196 * First element (16 bytes) of atomic wqe 197 */ 198 struct roce_sq_atomic_wqe_1st { 199 struct regpair remote_va; 200 __le32 xrc_srq; 201 u8 req_type; 202 u8 flags; 203 #define ROCE_SQ_ATOMIC_WQE_1ST_COMP_FLG_MASK 0x1 204 #define ROCE_SQ_ATOMIC_WQE_1ST_COMP_FLG_SHIFT 0 205 #define ROCE_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_MASK 0x1 206 #define ROCE_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_SHIFT 1 207 #define ROCE_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_MASK 0x1 208 #define ROCE_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_SHIFT 2 209 #define ROCE_SQ_ATOMIC_WQE_1ST_SE_FLG_MASK 0x1 210 #define ROCE_SQ_ATOMIC_WQE_1ST_SE_FLG_SHIFT 3 211 #define ROCE_SQ_ATOMIC_WQE_1ST_INLINE_FLG_MASK 0x1 212 #define ROCE_SQ_ATOMIC_WQE_1ST_INLINE_FLG_SHIFT 4 213 #define ROCE_SQ_ATOMIC_WQE_1ST_RESERVED0_MASK 0x7 214 #define ROCE_SQ_ATOMIC_WQE_1ST_RESERVED0_SHIFT 5 215 u8 reserved1; 216 u8 prev_wqe_size; 217 }; 218 219 /* 220 * Second element (16 bytes) of atomic wqe 221 */ 222 struct roce_sq_atomic_wqe_2nd { 223 struct regpair swap_data; 224 __le32 r_key; 225 __le32 reserved2; 226 }; 227 228 /* 229 * Third element (16 bytes) of atomic wqe 230 */ 231 struct roce_sq_atomic_wqe_3rd { 232 struct regpair cmp_data; 233 struct regpair reserved3; 234 }; 235 236 struct roce_sq_bind_wqe { 237 struct regpair addr; 238 __le32 l_key; 239 u8 req_type; 240 u8 flags; 241 #define ROCE_SQ_BIND_WQE_COMP_FLG_MASK 0x1 242 #define ROCE_SQ_BIND_WQE_COMP_FLG_SHIFT 0 243 #define ROCE_SQ_BIND_WQE_RD_FENCE_FLG_MASK 0x1 244 #define ROCE_SQ_BIND_WQE_RD_FENCE_FLG_SHIFT 1 245 #define ROCE_SQ_BIND_WQE_INV_FENCE_FLG_MASK 0x1 246 #define ROCE_SQ_BIND_WQE_INV_FENCE_FLG_SHIFT 2 247 #define ROCE_SQ_BIND_WQE_SE_FLG_MASK 0x1 248 #define ROCE_SQ_BIND_WQE_SE_FLG_SHIFT 3 249 #define ROCE_SQ_BIND_WQE_INLINE_FLG_MASK 0x1 250 #define ROCE_SQ_BIND_WQE_INLINE_FLG_SHIFT 4 251 #define ROCE_SQ_BIND_WQE_RESERVED0_MASK 0x7 252 #define ROCE_SQ_BIND_WQE_RESERVED0_SHIFT 5 253 u8 access_ctrl; 254 #define ROCE_SQ_BIND_WQE_REMOTE_READ_MASK 0x1 255 #define ROCE_SQ_BIND_WQE_REMOTE_READ_SHIFT 0 256 #define ROCE_SQ_BIND_WQE_REMOTE_WRITE_MASK 0x1 257 #define ROCE_SQ_BIND_WQE_REMOTE_WRITE_SHIFT 1 258 #define ROCE_SQ_BIND_WQE_ENABLE_ATOMIC_MASK 0x1 259 #define ROCE_SQ_BIND_WQE_ENABLE_ATOMIC_SHIFT 2 260 #define ROCE_SQ_BIND_WQE_LOCAL_READ_MASK 0x1 261 #define ROCE_SQ_BIND_WQE_LOCAL_READ_SHIFT 3 262 #define ROCE_SQ_BIND_WQE_LOCAL_WRITE_MASK 0x1 263 #define ROCE_SQ_BIND_WQE_LOCAL_WRITE_SHIFT 4 264 #define ROCE_SQ_BIND_WQE_RESERVED1_MASK 0x7 265 #define ROCE_SQ_BIND_WQE_RESERVED1_SHIFT 5 266 u8 prev_wqe_size; 267 u8 bind_ctrl; 268 #define ROCE_SQ_BIND_WQE_ZERO_BASED_MASK 0x1 269 #define ROCE_SQ_BIND_WQE_ZERO_BASED_SHIFT 0 270 #define ROCE_SQ_BIND_WQE_MW_TYPE_MASK 0x1 271 #define ROCE_SQ_BIND_WQE_MW_TYPE_SHIFT 1 272 #define ROCE_SQ_BIND_WQE_RESERVED2_MASK 0x3F 273 #define ROCE_SQ_BIND_WQE_RESERVED2_SHIFT 2 274 u8 reserved3[2]; 275 u8 length_hi; 276 __le32 length_lo; 277 __le32 parent_l_key; 278 __le32 reserved6; 279 }; 280 281 /* 282 * First element (16 bytes) of bind wqe 283 */ 284 struct roce_sq_bind_wqe_1st { 285 struct regpair addr; 286 __le32 l_key; 287 u8 req_type; 288 u8 flags; 289 #define ROCE_SQ_BIND_WQE_1ST_COMP_FLG_MASK 0x1 290 #define ROCE_SQ_BIND_WQE_1ST_COMP_FLG_SHIFT 0 291 #define ROCE_SQ_BIND_WQE_1ST_RD_FENCE_FLG_MASK 0x1 292 #define ROCE_SQ_BIND_WQE_1ST_RD_FENCE_FLG_SHIFT 1 293 #define ROCE_SQ_BIND_WQE_1ST_INV_FENCE_FLG_MASK 0x1 294 #define ROCE_SQ_BIND_WQE_1ST_INV_FENCE_FLG_SHIFT 2 295 #define ROCE_SQ_BIND_WQE_1ST_SE_FLG_MASK 0x1 296 #define ROCE_SQ_BIND_WQE_1ST_SE_FLG_SHIFT 3 297 #define ROCE_SQ_BIND_WQE_1ST_INLINE_FLG_MASK 0x1 298 #define ROCE_SQ_BIND_WQE_1ST_INLINE_FLG_SHIFT 4 299 #define ROCE_SQ_BIND_WQE_1ST_RESERVED0_MASK 0x7 300 #define ROCE_SQ_BIND_WQE_1ST_RESERVED0_SHIFT 5 301 u8 access_ctrl; 302 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_READ_MASK 0x1 303 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_READ_SHIFT 0 304 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_WRITE_MASK 0x1 305 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_WRITE_SHIFT 1 306 #define ROCE_SQ_BIND_WQE_1ST_ENABLE_ATOMIC_MASK 0x1 307 #define ROCE_SQ_BIND_WQE_1ST_ENABLE_ATOMIC_SHIFT 2 308 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_READ_MASK 0x1 309 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_READ_SHIFT 3 310 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_WRITE_MASK 0x1 311 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_WRITE_SHIFT 4 312 #define ROCE_SQ_BIND_WQE_1ST_RESERVED1_MASK 0x7 313 #define ROCE_SQ_BIND_WQE_1ST_RESERVED1_SHIFT 5 314 u8 prev_wqe_size; 315 }; 316 317 /* 318 * Second element (16 bytes) of bind wqe 319 */ 320 struct roce_sq_bind_wqe_2nd { 321 u8 bind_ctrl; 322 #define ROCE_SQ_BIND_WQE_2ND_ZERO_BASED_MASK 0x1 323 #define ROCE_SQ_BIND_WQE_2ND_ZERO_BASED_SHIFT 0 324 #define ROCE_SQ_BIND_WQE_2ND_MW_TYPE_MASK 0x1 325 #define ROCE_SQ_BIND_WQE_2ND_MW_TYPE_SHIFT 1 326 #define ROCE_SQ_BIND_WQE_2ND_RESERVED2_MASK 0x3F 327 #define ROCE_SQ_BIND_WQE_2ND_RESERVED2_SHIFT 2 328 u8 reserved3[2]; 329 u8 length_hi; 330 __le32 length_lo; 331 __le32 parent_l_key; 332 __le32 reserved6; 333 }; 334 335 /* 336 * Structure with only the SQ WQE common fields. Size is of one SQ element (16B) 337 */ 338 struct roce_sq_common_wqe { 339 __le32 reserved1[3]; 340 u8 req_type; 341 u8 flags; 342 #define ROCE_SQ_COMMON_WQE_COMP_FLG_MASK 0x1 343 #define ROCE_SQ_COMMON_WQE_COMP_FLG_SHIFT 0 344 #define ROCE_SQ_COMMON_WQE_RD_FENCE_FLG_MASK 0x1 345 #define ROCE_SQ_COMMON_WQE_RD_FENCE_FLG_SHIFT 1 346 #define ROCE_SQ_COMMON_WQE_INV_FENCE_FLG_MASK 0x1 347 #define ROCE_SQ_COMMON_WQE_INV_FENCE_FLG_SHIFT 2 348 #define ROCE_SQ_COMMON_WQE_SE_FLG_MASK 0x1 349 #define ROCE_SQ_COMMON_WQE_SE_FLG_SHIFT 3 350 #define ROCE_SQ_COMMON_WQE_INLINE_FLG_MASK 0x1 351 #define ROCE_SQ_COMMON_WQE_INLINE_FLG_SHIFT 4 352 #define ROCE_SQ_COMMON_WQE_RESERVED0_MASK 0x7 353 #define ROCE_SQ_COMMON_WQE_RESERVED0_SHIFT 5 354 u8 reserved2; 355 u8 prev_wqe_size; 356 }; 357 358 struct roce_sq_fmr_wqe { 359 struct regpair addr; 360 __le32 l_key; 361 u8 req_type; 362 u8 flags; 363 #define ROCE_SQ_FMR_WQE_COMP_FLG_MASK 0x1 364 #define ROCE_SQ_FMR_WQE_COMP_FLG_SHIFT 0 365 #define ROCE_SQ_FMR_WQE_RD_FENCE_FLG_MASK 0x1 366 #define ROCE_SQ_FMR_WQE_RD_FENCE_FLG_SHIFT 1 367 #define ROCE_SQ_FMR_WQE_INV_FENCE_FLG_MASK 0x1 368 #define ROCE_SQ_FMR_WQE_INV_FENCE_FLG_SHIFT 2 369 #define ROCE_SQ_FMR_WQE_SE_FLG_MASK 0x1 370 #define ROCE_SQ_FMR_WQE_SE_FLG_SHIFT 3 371 #define ROCE_SQ_FMR_WQE_INLINE_FLG_MASK 0x1 372 #define ROCE_SQ_FMR_WQE_INLINE_FLG_SHIFT 4 373 #define ROCE_SQ_FMR_WQE_RESERVED0_MASK 0x7 374 #define ROCE_SQ_FMR_WQE_RESERVED0_SHIFT 5 375 u8 access_ctrl; 376 #define ROCE_SQ_FMR_WQE_REMOTE_READ_MASK 0x1 377 #define ROCE_SQ_FMR_WQE_REMOTE_READ_SHIFT 0 378 #define ROCE_SQ_FMR_WQE_REMOTE_WRITE_MASK 0x1 379 #define ROCE_SQ_FMR_WQE_REMOTE_WRITE_SHIFT 1 380 #define ROCE_SQ_FMR_WQE_ENABLE_ATOMIC_MASK 0x1 381 #define ROCE_SQ_FMR_WQE_ENABLE_ATOMIC_SHIFT 2 382 #define ROCE_SQ_FMR_WQE_LOCAL_READ_MASK 0x1 383 #define ROCE_SQ_FMR_WQE_LOCAL_READ_SHIFT 3 384 #define ROCE_SQ_FMR_WQE_LOCAL_WRITE_MASK 0x1 385 #define ROCE_SQ_FMR_WQE_LOCAL_WRITE_SHIFT 4 386 #define ROCE_SQ_FMR_WQE_RESERVED1_MASK 0x7 387 #define ROCE_SQ_FMR_WQE_RESERVED1_SHIFT 5 388 u8 prev_wqe_size; 389 u8 fmr_ctrl; 390 #define ROCE_SQ_FMR_WQE_PAGE_SIZE_LOG_MASK 0x1F 391 #define ROCE_SQ_FMR_WQE_PAGE_SIZE_LOG_SHIFT 0 392 #define ROCE_SQ_FMR_WQE_ZERO_BASED_MASK 0x1 393 #define ROCE_SQ_FMR_WQE_ZERO_BASED_SHIFT 5 394 #define ROCE_SQ_FMR_WQE_BIND_EN_MASK 0x1 395 #define ROCE_SQ_FMR_WQE_BIND_EN_SHIFT 6 396 #define ROCE_SQ_FMR_WQE_RESERVED2_MASK 0x1 397 #define ROCE_SQ_FMR_WQE_RESERVED2_SHIFT 7 398 u8 reserved3[2]; 399 u8 length_hi; 400 __le32 length_lo; 401 struct regpair pbl_addr; 402 }; 403 404 /* 405 * First element (16 bytes) of fmr wqe 406 */ 407 struct roce_sq_fmr_wqe_1st { 408 struct regpair addr; 409 __le32 l_key; 410 u8 req_type; 411 u8 flags; 412 #define ROCE_SQ_FMR_WQE_1ST_COMP_FLG_MASK 0x1 413 #define ROCE_SQ_FMR_WQE_1ST_COMP_FLG_SHIFT 0 414 #define ROCE_SQ_FMR_WQE_1ST_RD_FENCE_FLG_MASK 0x1 415 #define ROCE_SQ_FMR_WQE_1ST_RD_FENCE_FLG_SHIFT 1 416 #define ROCE_SQ_FMR_WQE_1ST_INV_FENCE_FLG_MASK 0x1 417 #define ROCE_SQ_FMR_WQE_1ST_INV_FENCE_FLG_SHIFT 2 418 #define ROCE_SQ_FMR_WQE_1ST_SE_FLG_MASK 0x1 419 #define ROCE_SQ_FMR_WQE_1ST_SE_FLG_SHIFT 3 420 #define ROCE_SQ_FMR_WQE_1ST_INLINE_FLG_MASK 0x1 421 #define ROCE_SQ_FMR_WQE_1ST_INLINE_FLG_SHIFT 4 422 #define ROCE_SQ_FMR_WQE_1ST_RESERVED0_MASK 0x7 423 #define ROCE_SQ_FMR_WQE_1ST_RESERVED0_SHIFT 5 424 u8 access_ctrl; 425 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_READ_MASK 0x1 426 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_READ_SHIFT 0 427 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_WRITE_MASK 0x1 428 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_WRITE_SHIFT 1 429 #define ROCE_SQ_FMR_WQE_1ST_ENABLE_ATOMIC_MASK 0x1 430 #define ROCE_SQ_FMR_WQE_1ST_ENABLE_ATOMIC_SHIFT 2 431 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_READ_MASK 0x1 432 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_READ_SHIFT 3 433 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_WRITE_MASK 0x1 434 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_WRITE_SHIFT 4 435 #define ROCE_SQ_FMR_WQE_1ST_RESERVED1_MASK 0x7 436 #define ROCE_SQ_FMR_WQE_1ST_RESERVED1_SHIFT 5 437 u8 prev_wqe_size; 438 }; 439 440 /* 441 * Second element (16 bytes) of fmr wqe 442 */ 443 struct roce_sq_fmr_wqe_2nd { 444 u8 fmr_ctrl; 445 #define ROCE_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_MASK 0x1F 446 #define ROCE_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_SHIFT 0 447 #define ROCE_SQ_FMR_WQE_2ND_ZERO_BASED_MASK 0x1 448 #define ROCE_SQ_FMR_WQE_2ND_ZERO_BASED_SHIFT 5 449 #define ROCE_SQ_FMR_WQE_2ND_BIND_EN_MASK 0x1 450 #define ROCE_SQ_FMR_WQE_2ND_BIND_EN_SHIFT 6 451 #define ROCE_SQ_FMR_WQE_2ND_RESERVED2_MASK 0x1 452 #define ROCE_SQ_FMR_WQE_2ND_RESERVED2_SHIFT 7 453 u8 reserved3[2]; 454 u8 length_hi; 455 __le32 length_lo; 456 struct regpair pbl_addr; 457 }; 458 459 struct roce_sq_local_inv_wqe { 460 struct regpair reserved; 461 __le32 inv_l_key; 462 u8 req_type; 463 u8 flags; 464 #define ROCE_SQ_LOCAL_INV_WQE_COMP_FLG_MASK 0x1 465 #define ROCE_SQ_LOCAL_INV_WQE_COMP_FLG_SHIFT 0 466 #define ROCE_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_MASK 0x1 467 #define ROCE_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_SHIFT 1 468 #define ROCE_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_MASK 0x1 469 #define ROCE_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_SHIFT 2 470 #define ROCE_SQ_LOCAL_INV_WQE_SE_FLG_MASK 0x1 471 #define ROCE_SQ_LOCAL_INV_WQE_SE_FLG_SHIFT 3 472 #define ROCE_SQ_LOCAL_INV_WQE_INLINE_FLG_MASK 0x1 473 #define ROCE_SQ_LOCAL_INV_WQE_INLINE_FLG_SHIFT 4 474 #define ROCE_SQ_LOCAL_INV_WQE_RESERVED0_MASK 0x7 475 #define ROCE_SQ_LOCAL_INV_WQE_RESERVED0_SHIFT 5 476 u8 reserved1; 477 u8 prev_wqe_size; 478 }; 479 480 struct roce_sq_rdma_wqe { 481 __le32 imm_data; 482 __le32 length; 483 __le32 xrc_srq; 484 u8 req_type; 485 u8 flags; 486 #define ROCE_SQ_RDMA_WQE_COMP_FLG_MASK 0x1 487 #define ROCE_SQ_RDMA_WQE_COMP_FLG_SHIFT 0 488 #define ROCE_SQ_RDMA_WQE_RD_FENCE_FLG_MASK 0x1 489 #define ROCE_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT 1 490 #define ROCE_SQ_RDMA_WQE_INV_FENCE_FLG_MASK 0x1 491 #define ROCE_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT 2 492 #define ROCE_SQ_RDMA_WQE_SE_FLG_MASK 0x1 493 #define ROCE_SQ_RDMA_WQE_SE_FLG_SHIFT 3 494 #define ROCE_SQ_RDMA_WQE_INLINE_FLG_MASK 0x1 495 #define ROCE_SQ_RDMA_WQE_INLINE_FLG_SHIFT 4 496 #define ROCE_SQ_RDMA_WQE_RESERVED0_MASK 0x7 497 #define ROCE_SQ_RDMA_WQE_RESERVED0_SHIFT 5 498 u8 wqe_size; 499 u8 prev_wqe_size; 500 struct regpair remote_va; 501 __le32 r_key; 502 __le32 reserved1; 503 }; 504 505 /* 506 * First element (16 bytes) of rdma wqe 507 */ 508 struct roce_sq_rdma_wqe_1st { 509 __le32 imm_data; 510 __le32 length; 511 __le32 xrc_srq; 512 u8 req_type; 513 u8 flags; 514 #define ROCE_SQ_RDMA_WQE_1ST_COMP_FLG_MASK 0x1 515 #define ROCE_SQ_RDMA_WQE_1ST_COMP_FLG_SHIFT 0 516 #define ROCE_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_MASK 0x1 517 #define ROCE_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_SHIFT 1 518 #define ROCE_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_MASK 0x1 519 #define ROCE_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_SHIFT 2 520 #define ROCE_SQ_RDMA_WQE_1ST_SE_FLG_MASK 0x1 521 #define ROCE_SQ_RDMA_WQE_1ST_SE_FLG_SHIFT 3 522 #define ROCE_SQ_RDMA_WQE_1ST_INLINE_FLG_MASK 0x1 523 #define ROCE_SQ_RDMA_WQE_1ST_INLINE_FLG_SHIFT 4 524 #define ROCE_SQ_RDMA_WQE_1ST_RESERVED0_MASK 0x7 525 #define ROCE_SQ_RDMA_WQE_1ST_RESERVED0_SHIFT 5 526 u8 wqe_size; 527 u8 prev_wqe_size; 528 }; 529 530 /* 531 * Second element (16 bytes) of rdma wqe 532 */ 533 struct roce_sq_rdma_wqe_2nd { 534 struct regpair remote_va; 535 __le32 r_key; 536 __le32 reserved1; 537 }; 538 539 /* 540 * SQ WQE req type enumeration 541 */ 542 enum roce_sq_req_type { 543 ROCE_SQ_REQ_TYPE_SEND, 544 ROCE_SQ_REQ_TYPE_SEND_WITH_IMM, 545 ROCE_SQ_REQ_TYPE_SEND_WITH_INVALIDATE, 546 ROCE_SQ_REQ_TYPE_RDMA_WR, 547 ROCE_SQ_REQ_TYPE_RDMA_WR_WITH_IMM, 548 ROCE_SQ_REQ_TYPE_RDMA_RD, 549 ROCE_SQ_REQ_TYPE_ATOMIC_CMP_AND_SWAP, 550 ROCE_SQ_REQ_TYPE_ATOMIC_ADD, 551 ROCE_SQ_REQ_TYPE_LOCAL_INVALIDATE, 552 ROCE_SQ_REQ_TYPE_FAST_MR, 553 ROCE_SQ_REQ_TYPE_BIND, 554 ROCE_SQ_REQ_TYPE_INVALID, 555 MAX_ROCE_SQ_REQ_TYPE 556 }; 557 558 struct roce_sq_send_wqe { 559 __le32 inv_key_or_imm_data; 560 __le32 length; 561 __le32 xrc_srq; 562 u8 req_type; 563 u8 flags; 564 #define ROCE_SQ_SEND_WQE_COMP_FLG_MASK 0x1 565 #define ROCE_SQ_SEND_WQE_COMP_FLG_SHIFT 0 566 #define ROCE_SQ_SEND_WQE_RD_FENCE_FLG_MASK 0x1 567 #define ROCE_SQ_SEND_WQE_RD_FENCE_FLG_SHIFT 1 568 #define ROCE_SQ_SEND_WQE_INV_FENCE_FLG_MASK 0x1 569 #define ROCE_SQ_SEND_WQE_INV_FENCE_FLG_SHIFT 2 570 #define ROCE_SQ_SEND_WQE_SE_FLG_MASK 0x1 571 #define ROCE_SQ_SEND_WQE_SE_FLG_SHIFT 3 572 #define ROCE_SQ_SEND_WQE_INLINE_FLG_MASK 0x1 573 #define ROCE_SQ_SEND_WQE_INLINE_FLG_SHIFT 4 574 #define ROCE_SQ_SEND_WQE_RESERVED0_MASK 0x7 575 #define ROCE_SQ_SEND_WQE_RESERVED0_SHIFT 5 576 u8 wqe_size; 577 u8 prev_wqe_size; 578 }; 579 580 struct roce_sq_sge { 581 __le32 length; 582 struct regpair addr; 583 __le32 l_key; 584 }; 585 586 struct roce_srq_prod { 587 __le16 prod; 588 }; 589 590 struct roce_srq_sge { 591 struct regpair addr; 592 __le32 length; 593 __le32 l_key; 594 struct regpair wr_id; 595 u8 flags; 596 #define ROCE_SRQ_SGE_NUM_SGES_MASK 0x3 597 #define ROCE_SRQ_SGE_NUM_SGES_SHIFT 0 598 #define ROCE_SRQ_SGE_RESERVED0_MASK 0x3F 599 #define ROCE_SRQ_SGE_RESERVED0_SHIFT 2 600 u8 reserved1; 601 __le16 reserved2; 602 __le32 reserved3; 603 }; 604 605 /* 606 * RoCE doorbell data for SQ and RQ 607 */ 608 struct roce_pwm_val16_data { 609 __le16 icid; 610 __le16 prod_val; 611 }; 612 613 union roce_pwm_val16_data_union { 614 struct roce_pwm_val16_data as_struct; 615 __le32 as_dword; 616 }; 617 618 /* 619 * RoCE doorbell data for CQ 620 */ 621 struct roce_pwm_val32_data { 622 __le16 icid; 623 u8 agg_flags; 624 u8 params; 625 #define ROCE_PWM_VAL32_DATA_AGG_CMD_MASK 0x3 626 #define ROCE_PWM_VAL32_DATA_AGG_CMD_SHIFT 0 627 #define ROCE_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1 628 #define ROCE_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2 629 #define ROCE_PWM_VAL32_DATA_RESERVED_MASK 0x1F 630 #define ROCE_PWM_VAL32_DATA_RESERVED_SHIFT 3 631 __le32 cq_cons_val; 632 }; 633 634 union roce_pwm_val32_data_union { 635 struct roce_pwm_val32_data as_struct; 636 struct regpair as_repair; 637 }; 638 639 #endif /* __QLNXR_ROCE_H__ */ 640