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Searched refs:RLo (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrInfo.td4441 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4443 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4446 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4448 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4452 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4455 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4468 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
4470 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4472 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4477 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
[all …]
H A DARMInstrThumb2.td705 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
707 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
3239 def : Thumb2DSPPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
3240 (t2SMLALBB $Rn, $Rm, $RLo, $RHi)>;
3241 def : Thumb2DSPPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
3242 (t2SMLALBT $Rn, $Rm, $RLo, $RHi)>;
3243 def : Thumb2DSPPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
3244 (t2SMLALTB $Rn, $Rm, $RLo, $RHi)>;
3245 def : Thumb2DSPPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
3246 (t2SMLALTT $Rn, $Rm, $RLo, $RHi)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DConstantRange.cpp1562 auto RLo = RHS.getLower(); in estimateBitMaskedAndLowerBound() local
1566 auto Mask = ~((LLo ^ LHi) | (RLo ^ RHi) | (LLo ^ RLo)); in estimateBitMaskedAndLowerBound()
1578 auto LowerBoundByLHS = estimateBound(LLo, RLo, RHi); in estimateBitMaskedAndLowerBound()
1579 auto LowerBoundByRHS = estimateBound(RLo, LLo, LHi); in estimateBitMaskedAndLowerBound()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp29572 SDValue RLo = DAG.getNode(X86ISD::VPMADDUBSW, dl, ExVT, A, BLo); in LowerMUL() local
29574 RLo = DAG.getNode(ISD::AND, dl, VT, DAG.getBitcast(VT, RLo), Mask); in LowerMUL()
29577 return DAG.getNode(ISD::OR, dl, VT, RLo, DAG.getBitcast(VT, RHi)); in LowerMUL()
29610 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo); in LowerMUL() local
29612 return getPack(DAG, Subtarget, dl, VT, RLo, RHi); in LowerMUL()
29762 SDValue RLo = DAG.getNode(MulOpc, dl, ExVT, ALo, BLo); in LowervXi8MulWithUNPCK() local
29766 *Low = getPack(DAG, Subtarget, dl, VT, RLo, RHi); in LowervXi8MulWithUNPCK()
29768 return getPack(DAG, Subtarget, dl, VT, RLo, RHi, /*PackHiHalf*/ true); in LowervXi8MulWithUNPCK()
31032 SDValue RLo = getUnpackl(DAG, dl, VT, DAG.getUNDEF(VT), R); in LowerShift() local
31036 RLo = DAG.getBitcast(ExtVT, RLo); in LowerShift()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2798 SDValue RLo = DAG.getNode(Opcode, DL, MVT::i32, {Mid, Low, NewAmt}); in expandFSH64() local
2800 return DAG.getNode(NVPTXISD::BUILD_VECTOR, DL, MVT::i64, {RLo, RHi}); in expandFSH64()