1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
33 #include <sys/socket.h>
34
35 #include <machine/bus.h>
36
37 #include <net/if.h>
38 #include <net/if_media.h>
39
40 #include <dev/mii/miivar.h>
41
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
44
45 #include <dev/clk/clk.h>
46 #include <dev/hwreset/hwreset.h>
47 #include <dev/regulator/regulator.h>
48 #include <dev/syscon/syscon.h>
49
50 #include <dev/dwc/if_dwcvar.h>
51 #include <dev/dwc/dwc1000_reg.h>
52
53 #include "if_dwc_if.h"
54 #include "syscon_if.h"
55
56 #define RK3328_GRF_MAC_CON0 0x0900
57 #define MAC_CON0_GMAC2IO_TX_DL_CFG_MASK 0x7F
58 #define MAC_CON0_GMAC2IO_TX_DL_CFG_SHIFT 0
59 #define MAC_CON0_GMAC2IO_RX_DL_CFG_MASK 0x7F
60 #define MAC_CON0_GMAC2IO_RX_DL_CFG_SHIFT 7
61
62 #define RK3328_GRF_MAC_CON1 0x0904
63 #define MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA (1 << 0)
64 #define MAC_CON1_GMAC2IO_GMAC_RXCLK_DLY_ENA (1 << 1)
65 #define MAC_CON1_GMAC2IO_GMII_CLK_SEL_MASK (3 << 11)
66 #define MAC_CON1_GMAC2IO_GMII_CLK_SEL_125 (0 << 11)
67 #define MAC_CON1_GMAC2IO_GMII_CLK_SEL_25 (3 << 11)
68 #define MAC_CON1_GMAC2IO_GMII_CLK_SEL_2_5 (2 << 11)
69 #define MAC_CON1_GMAC2IO_RMII_MODE_MASK (1 << 9)
70 #define MAC_CON1_GMAC2IO_RMII_MODE (1 << 9)
71 #define MAC_CON1_GMAC2IO_INTF_SEL_MASK (7 << 4)
72 #define MAC_CON1_GMAC2IO_INTF_RMII (4 << 4)
73 #define MAC_CON1_GMAC2IO_INTF_RGMII (1 << 4)
74 #define MAC_CON1_GMAC2IO_RMII_CLK_SEL_MASK (1 << 7)
75 #define MAC_CON1_GMAC2IO_RMII_CLK_SEL_25 (1 << 7)
76 #define MAC_CON1_GMAC2IO_RMII_CLK_SEL_2_5 (0 << 7)
77 #define MAC_CON1_GMAC2IO_MAC_SPEED_MASK (1 << 2)
78 #define MAC_CON1_GMAC2IO_MAC_SPEED_100 (1 << 2)
79 #define MAC_CON1_GMAC2IO_MAC_SPEED_10 (0 << 2)
80 #define RK3328_GRF_MAC_CON2 0x0908
81 #define RK3328_GRF_MACPHY_CON0 0x0B00
82 #define MACPHY_CON0_CLK_50M_MASK (1 << 14)
83 #define MACPHY_CON0_CLK_50M (1 << 14)
84 #define MACPHY_CON0_RMII_MODE_MASK (3 << 6)
85 #define MACPHY_CON0_RMII_MODE (1 << 6)
86 #define RK3328_GRF_MACPHY_CON1 0x0B04
87 #define MACPHY_CON1_RMII_MODE_MASK (1 << 9)
88 #define MACPHY_CON1_RMII_MODE (1 << 9)
89 #define RK3328_GRF_MACPHY_CON2 0x0B08
90 #define RK3328_GRF_MACPHY_CON3 0x0B0C
91 #define RK3328_GRF_MACPHY_STATUS 0x0B10
92
93 #define RK3399_GRF_SOC_CON5 0xc214
94 #define SOC_CON5_GMAC_CLK_SEL_MASK (3 << 4)
95 #define SOC_CON5_GMAC_CLK_SEL_125 (0 << 4)
96 #define SOC_CON5_GMAC_CLK_SEL_25 (3 << 4)
97 #define SOC_CON5_GMAC_CLK_SEL_2_5 (2 << 4)
98 #define RK3399_GRF_SOC_CON6 0xc218
99 #define SOC_CON6_GMAC_TXCLK_DLY_ENA (1 << 7)
100 #define SOC_CON6_TX_DL_CFG_MASK 0x7F
101 #define SOC_CON6_TX_DL_CFG_SHIFT 0
102 #define SOC_CON6_RX_DL_CFG_MASK 0x7F
103 #define SOC_CON6_GMAC_RXCLK_DLY_ENA (1 << 15)
104 #define SOC_CON6_RX_DL_CFG_SHIFT 8
105
106 struct if_dwc_rk_softc;
107
108 typedef void (*if_dwc_rk_set_delaysfn_t)(struct if_dwc_rk_softc *);
109 typedef int (*if_dwc_rk_set_speedfn_t)(struct if_dwc_rk_softc *, int);
110 typedef void (*if_dwc_rk_set_phy_modefn_t)(struct if_dwc_rk_softc *);
111 typedef void (*if_dwc_rk_phy_powerupfn_t)(struct if_dwc_rk_softc *);
112
113 struct if_dwc_rk_ops {
114 if_dwc_rk_set_delaysfn_t set_delays;
115 if_dwc_rk_set_speedfn_t set_speed;
116 if_dwc_rk_set_phy_modefn_t set_phy_mode;
117 if_dwc_rk_phy_powerupfn_t phy_powerup;
118 };
119
120 struct if_dwc_rk_softc {
121 struct dwc_softc base;
122 uint32_t tx_delay;
123 uint32_t rx_delay;
124 bool integrated_phy;
125 bool clock_in;
126 phandle_t phy_node;
127 struct syscon *grf;
128 struct if_dwc_rk_ops *ops;
129 /* Common clocks */
130 clk_t mac_clk_rx;
131 clk_t mac_clk_tx;
132 clk_t aclk_mac;
133 clk_t pclk_mac;
134 clk_t clk_stmmaceth;
135 clk_t clk_mac_speed;
136 /* RMII clocks */
137 clk_t clk_mac_ref;
138 clk_t clk_mac_refout;
139 /* PHY clock */
140 clk_t clk_phy;
141 };
142
143 static void rk3328_set_delays(struct if_dwc_rk_softc *sc);
144 static int rk3328_set_speed(struct if_dwc_rk_softc *sc, int speed);
145 static void rk3328_set_phy_mode(struct if_dwc_rk_softc *sc);
146 static void rk3328_phy_powerup(struct if_dwc_rk_softc *sc);
147
148 static void rk3399_set_delays(struct if_dwc_rk_softc *sc);
149 static int rk3399_set_speed(struct if_dwc_rk_softc *sc, int speed);
150
151 static struct if_dwc_rk_ops rk3288_ops = {
152 };
153
154 static struct if_dwc_rk_ops rk3328_ops = {
155 .set_delays = rk3328_set_delays,
156 .set_speed = rk3328_set_speed,
157 .set_phy_mode = rk3328_set_phy_mode,
158 .phy_powerup = rk3328_phy_powerup,
159 };
160
161 static struct if_dwc_rk_ops rk3399_ops = {
162 .set_delays = rk3399_set_delays,
163 .set_speed = rk3399_set_speed,
164 };
165
166 static struct ofw_compat_data compat_data[] = {
167 {"rockchip,rk3288-gmac", (uintptr_t)&rk3288_ops},
168 {"rockchip,rk3328-gmac", (uintptr_t)&rk3328_ops},
169 {"rockchip,rk3399-gmac", (uintptr_t)&rk3399_ops},
170 {NULL, 0}
171 };
172
173 static void
rk3328_set_delays(struct if_dwc_rk_softc * sc)174 rk3328_set_delays(struct if_dwc_rk_softc *sc)
175 {
176 uint32_t reg;
177 uint32_t tx, rx;
178
179 if (!mii_contype_is_rgmii(sc->base.phy_mode))
180 return;
181
182 reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON0);
183 tx = ((reg >> MAC_CON0_GMAC2IO_TX_DL_CFG_SHIFT) & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK);
184 rx = ((reg >> MAC_CON0_GMAC2IO_RX_DL_CFG_SHIFT) & MAC_CON0_GMAC2IO_RX_DL_CFG_MASK);
185
186 reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON1);
187 if (bootverbose) {
188 device_printf(sc->base.dev, "current delays settings: tx=%u(%s) rx=%u(%s)\n",
189 tx, ((reg & MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA) ? "enabled" : "disabled"),
190 rx, ((reg & MAC_CON1_GMAC2IO_GMAC_RXCLK_DLY_ENA) ? "enabled" : "disabled"));
191
192 device_printf(sc->base.dev, "setting new RK3328 RX/TX delays: %d/%d\n",
193 sc->tx_delay, sc->rx_delay);
194 }
195
196 reg = (MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA | MAC_CON1_GMAC2IO_GMAC_RXCLK_DLY_ENA) << 16;
197 reg |= (MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA | MAC_CON1_GMAC2IO_GMAC_RXCLK_DLY_ENA);
198 SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1, reg);
199
200 reg = 0xffff << 16;
201 reg |= ((sc->tx_delay & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK) <<
202 MAC_CON0_GMAC2IO_TX_DL_CFG_SHIFT);
203 reg |= ((sc->rx_delay & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK) <<
204 MAC_CON0_GMAC2IO_RX_DL_CFG_SHIFT);
205 SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON0, reg);
206 }
207
208 static int
rk3328_set_speed(struct if_dwc_rk_softc * sc,int speed)209 rk3328_set_speed(struct if_dwc_rk_softc *sc, int speed)
210 {
211 uint32_t reg;
212
213 switch (sc->base.phy_mode) {
214 case MII_CONTYPE_RGMII:
215 case MII_CONTYPE_RGMII_ID:
216 case MII_CONTYPE_RGMII_RXID:
217 case MII_CONTYPE_RGMII_TXID:
218 switch (speed) {
219 case IFM_1000_T:
220 case IFM_1000_SX:
221 reg = MAC_CON1_GMAC2IO_GMII_CLK_SEL_125;
222 break;
223 case IFM_100_TX:
224 reg = MAC_CON1_GMAC2IO_GMII_CLK_SEL_25;
225 break;
226 case IFM_10_T:
227 reg = MAC_CON1_GMAC2IO_GMII_CLK_SEL_2_5;
228 break;
229 default:
230 device_printf(sc->base.dev, "unsupported RGMII media %u\n", speed);
231 return (-1);
232 }
233
234 SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1,
235 ((MAC_CON1_GMAC2IO_GMII_CLK_SEL_MASK << 16) | reg));
236 break;
237 case MII_CONTYPE_RMII:
238 switch (speed) {
239 case IFM_100_TX:
240 reg = MAC_CON1_GMAC2IO_RMII_CLK_SEL_25 |
241 MAC_CON1_GMAC2IO_MAC_SPEED_100;
242 break;
243 case IFM_10_T:
244 reg = MAC_CON1_GMAC2IO_RMII_CLK_SEL_2_5 |
245 MAC_CON1_GMAC2IO_MAC_SPEED_10;
246 break;
247 default:
248 device_printf(sc->base.dev, "unsupported RMII media %u\n", speed);
249 return (-1);
250 }
251
252 SYSCON_WRITE_4(sc->grf,
253 sc->integrated_phy ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1,
254 reg |
255 ((MAC_CON1_GMAC2IO_RMII_CLK_SEL_MASK | MAC_CON1_GMAC2IO_MAC_SPEED_MASK) << 16));
256 break;
257 }
258
259 return (0);
260 }
261
262 static void
rk3328_set_phy_mode(struct if_dwc_rk_softc * sc)263 rk3328_set_phy_mode(struct if_dwc_rk_softc *sc)
264 {
265
266 switch (sc->base.phy_mode) {
267 case MII_CONTYPE_RGMII:
268 case MII_CONTYPE_RGMII_ID:
269 case MII_CONTYPE_RGMII_RXID:
270 case MII_CONTYPE_RGMII_TXID:
271 SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1,
272 ((MAC_CON1_GMAC2IO_INTF_SEL_MASK | MAC_CON1_GMAC2IO_RMII_MODE_MASK) << 16) |
273 MAC_CON1_GMAC2IO_INTF_RGMII);
274 break;
275 case MII_CONTYPE_RMII:
276 SYSCON_WRITE_4(sc->grf, sc->integrated_phy ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1,
277 ((MAC_CON1_GMAC2IO_INTF_SEL_MASK | MAC_CON1_GMAC2IO_RMII_MODE_MASK) << 16) |
278 MAC_CON1_GMAC2IO_INTF_RMII | MAC_CON1_GMAC2IO_RMII_MODE);
279 break;
280 }
281 }
282
283 static void
rk3328_phy_powerup(struct if_dwc_rk_softc * sc)284 rk3328_phy_powerup(struct if_dwc_rk_softc *sc)
285 {
286 SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON1,
287 (MACPHY_CON1_RMII_MODE_MASK << 16) |
288 MACPHY_CON1_RMII_MODE);
289 }
290
291 static void
rk3399_set_delays(struct if_dwc_rk_softc * sc)292 rk3399_set_delays(struct if_dwc_rk_softc *sc)
293 {
294 uint32_t reg, tx, rx;
295
296 if (!mii_contype_is_rgmii(sc->base.phy_mode))
297 return;
298
299 reg = SYSCON_READ_4(sc->grf, RK3399_GRF_SOC_CON6);
300 tx = ((reg >> SOC_CON6_TX_DL_CFG_SHIFT) & SOC_CON6_TX_DL_CFG_MASK);
301 rx = ((reg >> SOC_CON6_RX_DL_CFG_SHIFT) & SOC_CON6_RX_DL_CFG_MASK);
302
303 if (bootverbose) {
304 device_printf(sc->base.dev, "current delays settings: tx=%u(%s) rx=%u(%s)\n",
305 tx, ((reg & SOC_CON6_GMAC_TXCLK_DLY_ENA) ? "enabled" : "disabled"),
306 rx, ((reg & SOC_CON6_GMAC_RXCLK_DLY_ENA) ? "enabled" : "disabled"));
307
308 device_printf(sc->base.dev, "setting new RK3399 RX/TX delays: %d/%d\n",
309 sc->rx_delay, sc->tx_delay);
310 }
311
312 reg = 0xFFFF << 16;
313 reg |= ((sc->tx_delay & SOC_CON6_TX_DL_CFG_MASK) <<
314 SOC_CON6_TX_DL_CFG_SHIFT);
315 reg |= ((sc->rx_delay & SOC_CON6_RX_DL_CFG_MASK) <<
316 SOC_CON6_RX_DL_CFG_SHIFT);
317 reg |= SOC_CON6_GMAC_TXCLK_DLY_ENA | SOC_CON6_GMAC_RXCLK_DLY_ENA;
318
319 SYSCON_WRITE_4(sc->grf, RK3399_GRF_SOC_CON6, reg);
320 }
321
322 static int
rk3399_set_speed(struct if_dwc_rk_softc * sc,int speed)323 rk3399_set_speed(struct if_dwc_rk_softc *sc, int speed)
324 {
325 uint32_t reg;
326
327 switch (speed) {
328 case IFM_1000_T:
329 case IFM_1000_SX:
330 reg = SOC_CON5_GMAC_CLK_SEL_125;
331 break;
332 case IFM_100_TX:
333 reg = SOC_CON5_GMAC_CLK_SEL_25;
334 break;
335 case IFM_10_T:
336 reg = SOC_CON5_GMAC_CLK_SEL_2_5;
337 break;
338 default:
339 device_printf(sc->base.dev, "unsupported media %u\n", speed);
340 return (-1);
341 }
342
343 SYSCON_WRITE_4(sc->grf, RK3399_GRF_SOC_CON5,
344 ((SOC_CON5_GMAC_CLK_SEL_MASK << 16) | reg));
345 return (0);
346 }
347
348 static int
if_dwc_rk_sysctl_delays(SYSCTL_HANDLER_ARGS)349 if_dwc_rk_sysctl_delays(SYSCTL_HANDLER_ARGS)
350 {
351 struct if_dwc_rk_softc *sc;
352 int rv;
353 uint32_t rxtx;
354
355 sc = arg1;
356 rxtx = ((sc->rx_delay << 8) | sc->tx_delay);
357
358 rv = sysctl_handle_int(oidp, &rxtx, 0, req);
359 if (rv != 0 || req->newptr == NULL)
360 return (rv);
361 sc->tx_delay = rxtx & 0xff;
362 sc->rx_delay = (rxtx >> 8) & 0xff;
363
364 if (sc->ops->set_delays)
365 sc->ops->set_delays(sc);
366
367 return (0);
368 }
369
370 static int
if_dwc_rk_init_sysctl(struct if_dwc_rk_softc * sc)371 if_dwc_rk_init_sysctl(struct if_dwc_rk_softc *sc)
372 {
373 struct sysctl_oid *child;
374 struct sysctl_ctx_list *ctx_list;
375
376 ctx_list = device_get_sysctl_ctx(sc->base.dev);
377 child = device_get_sysctl_tree(sc->base.dev);
378 SYSCTL_ADD_PROC(ctx_list,
379 SYSCTL_CHILDREN(child), OID_AUTO, "delays",
380 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, sc, 0,
381 if_dwc_rk_sysctl_delays, "", "RGMII RX/TX delays: ((rx << 8) | tx)");
382
383 return (0);
384 }
385
386 static int
if_dwc_rk_probe(device_t dev)387 if_dwc_rk_probe(device_t dev)
388 {
389
390 if (!ofw_bus_status_okay(dev))
391 return (ENXIO);
392 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
393 return (ENXIO);
394 device_set_desc(dev, "Rockchip Gigabit Ethernet Controller");
395
396 return (BUS_PROBE_DEFAULT);
397 }
398
399 static int
if_dwc_rk_init_clocks(device_t dev)400 if_dwc_rk_init_clocks(device_t dev)
401 {
402 struct if_dwc_rk_softc *sc;
403
404 sc = device_get_softc(dev);
405
406 /* Enable clocks */
407
408 if (clk_get_by_ofw_name(dev, 0, "mac_clk_tx", &sc->mac_clk_tx) != 0) {
409 device_printf(sc->base.dev, "could not get mac_clk_tx clock\n");
410 sc->mac_clk_tx = NULL;
411 }
412
413 if (clk_get_by_ofw_name(dev, 0, "aclk_mac", &sc->aclk_mac) != 0) {
414 device_printf(sc->base.dev, "could not get aclk_mac clock\n");
415 sc->aclk_mac = NULL;
416 }
417
418 if (clk_get_by_ofw_name(dev, 0, "pclk_mac", &sc->pclk_mac) != 0) {
419 device_printf(sc->base.dev, "could not get pclk_mac clock\n");
420 sc->pclk_mac = NULL;
421 }
422
423 /* Optional clock */
424 clk_get_by_ofw_name(dev, 0, "clk_mac_speed", &sc->clk_mac_speed);
425
426 if (sc->base.phy_mode == MII_CONTYPE_RMII) {
427 if (clk_get_by_ofw_name(dev, 0, "mac_clk_rx", &sc->mac_clk_rx) != 0) {
428 device_printf(sc->base.dev, "could not get mac_clk_rx clock\n");
429 sc->mac_clk_rx = NULL;
430 }
431
432 if (clk_get_by_ofw_name(dev, 0, "clk_mac_ref", &sc->clk_mac_ref) != 0) {
433 device_printf(sc->base.dev, "could not get clk_mac_ref clock\n");
434 sc->clk_mac_ref = NULL;
435 }
436
437 if (!sc->clock_in) {
438 if (clk_get_by_ofw_name(dev, 0, "clk_mac_refout", &sc->clk_mac_refout) != 0) {
439 device_printf(sc->base.dev, "could not get clk_mac_refout clock\n");
440 sc->clk_mac_refout = NULL;
441 }
442
443 clk_set_freq(sc->clk_stmmaceth, 50000000, 0);
444 }
445 }
446
447 if ((sc->phy_node != 0) && sc->integrated_phy) {
448 if (clk_get_by_ofw_index(dev, sc->phy_node, 0, &sc->clk_phy) != 0) {
449 device_printf(sc->base.dev, "could not get PHY clock\n");
450 sc->clk_phy = NULL;
451 }
452
453 if (sc->clk_phy) {
454 clk_set_freq(sc->clk_phy, 50000000, 0);
455 }
456 }
457
458 if (sc->base.phy_mode == MII_CONTYPE_RMII) {
459 if (sc->mac_clk_rx)
460 clk_enable(sc->mac_clk_rx);
461 if (sc->clk_mac_ref)
462 clk_enable(sc->clk_mac_ref);
463 if (sc->clk_mac_refout)
464 clk_enable(sc->clk_mac_refout);
465 }
466 if (sc->clk_phy)
467 clk_enable(sc->clk_phy);
468 if (sc->aclk_mac)
469 clk_enable(sc->aclk_mac);
470 if (sc->pclk_mac)
471 clk_enable(sc->pclk_mac);
472 if (sc->mac_clk_tx)
473 clk_enable(sc->mac_clk_tx);
474 if (sc->clk_mac_speed)
475 clk_enable(sc->clk_mac_speed);
476
477 DELAY(50);
478
479 return (0);
480 }
481
482 static int
if_dwc_rk_init(device_t dev)483 if_dwc_rk_init(device_t dev)
484 {
485 struct if_dwc_rk_softc *sc;
486 phandle_t node;
487 uint32_t rx, tx;
488 int err;
489 pcell_t phy_handle;
490 char *clock_in_out;
491 hwreset_t phy_reset;
492 regulator_t phy_supply;
493
494 sc = device_get_softc(dev);
495 node = ofw_bus_get_node(dev);
496 sc->ops = (struct if_dwc_rk_ops *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
497 if (OF_hasprop(node, "rockchip,grf") &&
498 syscon_get_by_ofw_property(dev, node,
499 "rockchip,grf", &sc->grf) != 0) {
500 device_printf(dev, "cannot get grf driver handle\n");
501 return (ENXIO);
502 }
503
504 if (OF_getencprop(node, "tx_delay", &tx, sizeof(tx)) <= 0)
505 tx = 0x30;
506 if (OF_getencprop(node, "rx_delay", &rx, sizeof(rx)) <= 0)
507 rx = 0x10;
508 sc->tx_delay = tx;
509 sc->rx_delay = rx;
510
511 sc->clock_in = true;
512 if (OF_getprop_alloc(node, "clock_in_out", (void **)&clock_in_out)) {
513 if (strcmp(clock_in_out, "input") == 0)
514 sc->clock_in = true;
515 else
516 sc->clock_in = false;
517 OF_prop_free(clock_in_out);
518 }
519
520 if (OF_getencprop(node, "phy-handle", (void *)&phy_handle,
521 sizeof(phy_handle)) > 0)
522 sc->phy_node = OF_node_from_xref(phy_handle);
523
524 if (sc->phy_node)
525 sc->integrated_phy = OF_hasprop(sc->phy_node, "phy-is-integrated");
526
527 if (sc->integrated_phy)
528 device_printf(sc->base.dev, "PHY is integrated\n");
529
530 if_dwc_rk_init_clocks(dev);
531
532 if (sc->ops->set_phy_mode)
533 sc->ops->set_phy_mode(sc);
534
535 if (sc->ops->set_delays)
536 sc->ops->set_delays(sc);
537
538 /*
539 * this also sets delays if tunable is defined
540 */
541 err = if_dwc_rk_init_sysctl(sc);
542 if (err != 0)
543 return (err);
544
545 if (regulator_get_by_ofw_property(sc->base.dev, 0,
546 "phy-supply", &phy_supply) == 0) {
547 if (regulator_enable(phy_supply)) {
548 device_printf(sc->base.dev,
549 "cannot enable 'phy' regulator\n");
550 }
551 }
552 else
553 device_printf(sc->base.dev, "no phy-supply property\n");
554
555 /* Power up */
556 if (sc->integrated_phy) {
557 if (sc->ops->phy_powerup)
558 sc->ops->phy_powerup(sc);
559
560 SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON0,
561 (MACPHY_CON0_CLK_50M_MASK << 16) |
562 MACPHY_CON0_CLK_50M);
563 SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON0,
564 (MACPHY_CON0_RMII_MODE_MASK << 16) |
565 MACPHY_CON0_RMII_MODE);
566 SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON2, 0xffff1234);
567 SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON3, 0x003f0035);
568
569 if (hwreset_get_by_ofw_idx(dev, sc->phy_node, 0, &phy_reset) == 0) {
570 hwreset_assert(phy_reset);
571 DELAY(20);
572 hwreset_deassert(phy_reset);
573 DELAY(20);
574 }
575 }
576
577 return (0);
578 }
579
580 static int
if_dwc_rk_mii_clk(device_t dev)581 if_dwc_rk_mii_clk(device_t dev)
582 {
583 struct if_dwc_rk_softc *sc;
584 uint64_t freq;
585 int rv;
586
587 sc = device_get_softc(dev);
588 if ((rv = clk_get_freq(sc->pclk_mac, &freq)) != 0)
589 return (-rv);
590 freq = freq / 1000 / 1000;
591
592 if (freq >= 60 && freq <= 100)
593 return (GMAC_MII_CLK_60_100M_DIV42);
594 else if (freq >= 100 && freq <= 150)
595 return (GMAC_MII_CLK_100_150M_DIV62);
596 else if (freq >= 20 && freq <= 35)
597 return (GMAC_MII_CLK_25_35M_DIV16);
598 else if (freq >= 35 && freq <= 60)
599 return (GMAC_MII_CLK_35_60M_DIV26);
600 else if (freq >= 150 && freq <= 250)
601 return (GMAC_MII_CLK_150_250M_DIV102);
602 else if (freq >= 250 && freq <= 300)
603 return (GMAC_MII_CLK_250_300M_DIV124);
604
605 return (-ERANGE);
606 }
607
608 static int
if_dwc_rk_set_speed(device_t dev,int speed)609 if_dwc_rk_set_speed(device_t dev, int speed)
610 {
611 struct if_dwc_rk_softc *sc;
612
613 sc = device_get_softc(dev);
614
615 if (sc->ops->set_speed)
616 return sc->ops->set_speed(sc, speed);
617
618 return (0);
619 }
620
621 static device_method_t if_dwc_rk_methods[] = {
622 DEVMETHOD(device_probe, if_dwc_rk_probe),
623
624 DEVMETHOD(if_dwc_init, if_dwc_rk_init),
625 DEVMETHOD(if_dwc_mii_clk, if_dwc_rk_mii_clk),
626 DEVMETHOD(if_dwc_set_speed, if_dwc_rk_set_speed),
627
628 DEVMETHOD_END
629 };
630
631 extern driver_t dwc_driver;
632
633 DEFINE_CLASS_1(dwc, dwc_rk_driver, if_dwc_rk_methods,
634 sizeof(struct if_dwc_rk_softc), dwc_driver);
635 DRIVER_MODULE(dwc_rk, simplebus, dwc_rk_driver, 0, 0);
636 MODULE_DEPEND(dwc_rk, dwc, 1, 1, 1);
637