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Searched refs:RISCVVType (Results 1 – 21 of 21) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp124 RISCVVType::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI); in createInstruments()
128 case RISCVVType::LMUL_1: in createInstruments()
131 case RISCVVType::LMUL_2: in createInstruments()
134 case RISCVVType::LMUL_4: in createInstruments()
137 case RISCVVType::LMUL_8: in createInstruments()
140 case RISCVVType::LMUL_F2: in createInstruments()
143 case RISCVVType::LMUL_F4: in createInstruments()
146 case RISCVVType::LMUL_F8: in createInstruments()
149 case RISCVVType::LMUL_RESERVED: in createInstruments()
156 unsigned SEW = RISCVVType::getSEW(VTypeI); in createInstruments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp271 static bool isLMUL1OrSmaller(RISCVVType::VLMUL LMUL) { in isLMUL1OrSmaller()
272 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL); in isLMUL1OrSmaller()
285 if (RISCVVType::getSEW(CurVType) != RISCVVType::getSEW(NewVType)) in areCompatibleVTYPEs()
289 if (RISCVVType::getSEW(NewVType) < RISCVVType::getSEW(CurVType)) in areCompatibleVTYPEs()
293 if (RISCVVType::getSEW(NewVType) < RISCVVType::getSEW(CurVType) || in areCompatibleVTYPEs()
294 RISCVVType::getSEW(NewVType) >= 64) in areCompatibleVTYPEs()
303 if (RISCVVType::getVLMUL(CurVType) != RISCVVType::getVLMUL(NewVType)) in areCompatibleVTYPEs()
307 if (!isLMUL1OrSmaller(RISCVVType::getVLMUL(NewVType))) in areCompatibleVTYPEs()
313 auto Ratio1 = RISCVVType::getSEWLMULRatio(RISCVVType::getSEW(CurVType), in areCompatibleVTYPEs()
314 RISCVVType::getVLMUL(CurVType)); in areCompatibleVTYPEs()
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H A DRISCVVectorPeephole.cpp218 auto LMUL = RISCVVType::decodeVLMUL(RISCVII::getLMul(MI.getDesc().TSFlags)); in convertToVLMAX()
224 assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW"); in convertToVLMAX()
380 MachineOperand::CreateImm(RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED)); in convertAllOnesVMergeToVMv()
466 MachineOperand::CreateImm(RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED)); in convertSameMaskVMergeToVMv()
615 SrcPolicy.setImm(SrcPolicy.getImm() | RISCVVType::TAIL_AGNOSTIC); in foldUndefPassthruVMV_V_V()
685 int64_t Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED; in foldVMV_V_V()
686 if ((MI.getOperand(5).getImm() & RISCVVType::TAIL_AGNOSTIC) && in foldVMV_V_V()
688 Policy |= RISCVVType::TAIL_AGNOSTIC; in foldVMV_V_V()
786 uint64_t Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED; in foldVMergeToMask()
788 Policy |= RISCVVType::TAIL_AGNOSTIC; in foldVMergeToMask()
H A DRISCVISelDAGToDAG.cpp272 uint64_t Policy = RISCVVType::MASK_AGNOSTIC; in addVectorLoadStoreOperands()
287 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEG()
316 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEGFF()
346 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLXSEG()
361 auto DecodedLMUL = RISCVVType::decodeVLMUL(LMUL); in selectVLXSEG()
370 RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); in selectVLXSEG()
394 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSSEG()
419 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSXSEG()
434 auto DecodedLMUL = RISCVVType::decodeVLMUL(LMUL); in selectVSXSEG()
443 RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); in selectVSXSEG()
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H A DRISCVRegisterInfo.h46 static inline RISCVVType::VLMUL getLMul(uint8_t TSFlags) { in getLMul()
47 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulShiftMask) >> in getLMul()
H A DRISCVInstrInfo.cpp259 RISCVVType::VLMUL LMul) { in isConvertibleToVMV_V_V()
287 RISCVVType::VLMUL FirstLMul = RISCVVType::getVLMUL(FirstVType); in isConvertibleToVMV_V_V()
288 FirstSEW = RISCVVType::getSEW(FirstVType); in isConvertibleToVMV_V_V()
306 if (RISCVVType::getSEW(VType) != FirstSEW) in isConvertibleToVMV_V_V()
311 if (!RISCVVType::isTailAgnostic(VType)) in isConvertibleToVMV_V_V()
319 return LMul == RISCVVType::getVLMUL(VType); in isConvertibleToVMV_V_V()
386 RISCVVType::VLMUL LMul = RISCVRI::getLMul(RegClass->TSFlags); in copyPhysRegVector()
391 auto [LMulVal, Fractional] = RISCVVType::decodeVLMUL(LMul); in copyPhysRegVector()
405 -> std::tuple<RISCVVType::VLMUL, const TargetRegisterClass &, unsigned, in copyPhysRegVector()
417 return {RISCVVType::LMUL_8, RISCV::VRM8RegClass, RISCV::VMV8R_V, in copyPhysRegVector()
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H A DRISCVVectorMaskDAGMutation.cpp79 RISCVII::getLMul(MI->getDesc().TSFlags) != RISCVVType::LMUL_8) in apply()
H A DRISCVInterleavedAccess.cpp53 auto [LMUL, Fractional] = RISCVVType::decodeVLMUL(getLMUL(ContainerVT)); in isLegalInterleavedAccessType()
481 RISCVVType::TAIL_AGNOSTIC | RISCVVType::MASK_AGNOSTIC), in lowerInterleavedVPLoad()
H A DRISCVExpandPseudoInsts.cpp442 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false); in expandPseudoReadVLENBViaVSETVLIX0()
443 unsigned VTypeImm = RISCVVType::encodeVTYPE( in expandPseudoReadVLENBViaVSETVLIX0()
H A DRISCVVLOptimizer.cpp75 OperandInfo(RISCVVType::VLMUL EMUL, unsigned Log2EEW) in OperandInfo()
76 : EMUL(RISCVVType::decodeVLMUL(EMUL)), Log2EEW(Log2EEW) {} in OperandInfo()
144 RISCVVType::VLMUL MIVLMUL = RISCVII::getLMul(MI.getDesc().TSFlags); in getEMULEqualsEEWDivSEWTimesLMUL()
145 auto [MILMUL, MILMULIsFractional] = RISCVVType::decodeVLMUL(MIVLMUL); in getEMULEqualsEEWDivSEWTimesLMUL()
H A DRISCVISelLowering.cpp1190 if (getLMUL(VT) == RISCVVType::LMUL_8) { in RISCVTargetLowering()
2515 RISCVVType::VLMUL RISCVTargetLowering::getLMUL(MVT VT) { in getLMUL()
2519 return RISCVVType::LMUL_F8; in getLMUL()
2522 return RISCVVType::LMUL_F4; in getLMUL()
2525 return RISCVVType::LMUL_F2; in getLMUL()
2528 return RISCVVType::LMUL_1; in getLMUL()
2531 return RISCVVType::LMUL_2; in getLMUL()
2533 return RISCVVType::LMUL_4; in getLMUL()
2546 return RISCVVType::LMUL_F8; in getLMUL()
2548 return RISCVVType::LMUL_F4; in getLMUL()
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H A DRISCVISelLowering.h350 static RISCVVType::VLMUL getLMUL(MVT VT);
375 static unsigned getRegClassIDForLMUL(RISCVVType::VLMUL LMul);
H A DRISCVInstrInfoXSfmm.td30 return RISCVVType::isValidXSfmmVType(Imm);
H A DRISCVTargetTransformInfo.cpp920 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in isM1OrSmaller()
921 return (LMUL == RISCVVType::VLMUL::LMUL_F8 || in isM1OrSmaller()
922 LMUL == RISCVVType::VLMUL::LMUL_F4 || in isM1OrSmaller()
923 LMUL == RISCVVType::VLMUL::LMUL_F2 || in isM1OrSmaller()
924 LMUL == RISCVVType::VLMUL::LMUL_1); in isM1OrSmaller()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.cpp220 if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED || in printVTypeI()
221 RISCVVType::getSEW(Imm) > 64 || (Imm >> 8) != 0) { in printVTypeI()
226 RISCVVType::printVType(Imm, O); in printVTypeI()
233 assert(RISCVVType::isValidXSfmmVType(Imm)); in printXSfmmVType()
234 unsigned SEW = RISCVVType::getSEW(Imm); in printXSfmmVType()
236 bool AltFmt = RISCVVType::isAltFmt(Imm); in printXSfmmVType()
239 unsigned Widen = RISCVVType::getXSfmmWiden(Imm); in printXSfmmVType()
H A DRISCVBaseInfo.h150 static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) { in getLMul()
151 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift); in getLMul()
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVTargetParser.h72 namespace RISCVVType {
152 return (VTypeI & ~0x738) == 0 && RISCVVType::hasXSfmmWiden(VTypeI) && in isValidXSfmmVType()
153 RISCVVType::getSEW(VTypeI) * RISCVVType::getXSfmmWiden(VTypeI) <= 64; in isValidXSfmmVType()
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVTargetParser.cpp150 namespace RISCVVType { namespace
237 unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMul); in getSameRatioLMUL()
243 return RISCVVType::encodeLMUL(EMUL, Fractional); in getSameRatioLMUL()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp1122 RISCVVType::decodeVLMUL(RISCVTargetLowering::getLMUL(LitTyMVT)).second || in legalizeExtractSubvector()
1123 RISCVTargetLowering::getLMUL(LitTyMVT) == RISCVVType::LMUL_1); in legalizeExtractSubvector()
1146 uint64_t Policy = RISCVVType::TAIL_AGNOSTIC | RISCVVType::MASK_AGNOSTIC; in legalizeExtractSubvector()
1268 uint64_t Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED; in legalizeInsertSubvector()
1271 Policy = RISCVVType::TAIL_AGNOSTIC; in legalizeInsertSubvector()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp638 return Kind == KindTy::VType && RISCVVType::isValidXSfmmVType(VType.Val); in isXSfmmVType()
1052 RISCVVType::printVType(getVType(), OS); in print()
2260 if (!RISCVVType::isValidSEW(Sew)) in parseVTypeToken()
2279 if (!RISCVVType::isValidLMUL(Lmul, Fractional)) in parseVTypeToken()
2349 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional); in parseVTypeI()
2361 RISCVVType::encodeVTYPE(VLMUL, Sew, TailAgnostic, MaskAgnostic); in parseVTypeI()
2396 if (!RISCVVType::isValidSEW(SEW)) in parseXSfmmVType()
2420 RISCVVType::encodeXSfmmVType(SEW, Widen, AltFmt), S)); in parseXSfmmVType()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp2014 uint64_t SEW = RISCVVType::decodeVSEW( in computeKnownBitsFromOperator()
2016 RISCVVType::VLMUL VLMUL = static_cast<RISCVVType::VLMUL>( in computeKnownBitsFromOperator()
2020 uint64_t MaxVL = MaxVLEN / RISCVVType::getSEWLMULRatio(SEW, VLMUL); in computeKnownBitsFromOperator()