| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVSubtarget.cpp | 72 void RISCVSubtarget::anchor() {} in anchor()
74 RISCVSubtarget &
75 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, in initializeSubtargetDependencies()
98 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, in RISCVSubtarget() function in RISCVSubtarget
111 RISCVSubtarget::~RISCVSubtarget() = default;
113 const SelectionDAGTargetInfo *RISCVSubtarget::getSelectionDAGInfo() const { in getSelectionDAGInfo()
117 const CallLowering *RISCVSubtarget::getCallLowering() const { in getCallLowering()
123 InstructionSelector *RISCVSubtarget::getInstructionSelector() const { in getInstructionSelector()
132 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const { in getLegalizerInfo()
138 const RISCVRegisterBankInfo *RISCVSubtarget::getRegBankInfo() const { in getRegBankInfo()
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| H A D | RISCVMoveMerger.cpp | 48 bool mergeMoveSARegPair(const RISCVSubtarget &STI, MachineBasicBlock &MBB);
71 static unsigned getMoveFromAToSOpcode(const RISCVSubtarget &STI) { in getMoveFromAToSOpcode()
91 static unsigned getMoveFromSToAOpcode(const RISCVSubtarget &STI) { in getMoveFromSToAOpcode()
232 bool RISCVMoveMerge::mergeMoveSARegPair(const RISCVSubtarget &STI, in mergeMoveSARegPair()
271 const RISCVSubtarget *Subtarget = &Fn.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVTargetMachine.h | 25 mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;
34 const RISCVSubtarget *getSubtargetImpl(const Function &F) const override;
38 const RISCVSubtarget *getSubtargetImpl() const = delete;
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| H A D | RISCVOptWInstrs.cpp | 69 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
71 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
73 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
120 const RISCVSubtarget &ST, in hasAllNBitUsers()
365 static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, in hasAllWUsers()
416 static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST, in isSignExtendedW()
674 const RISCVSubtarget &ST, in removeSExtWInstrs()
726 const RISCVSubtarget &ST, in stripWSuffixes()
753 const RISCVSubtarget &ST, in appendWSuffixes()
808 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVMakeCompressible.cpp | 197 const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>(); in isCompressibleLoad()
222 const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>(); in isCompressibleStore()
414 const RISCVSubtarget &STI = Fn.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVMachineFunctionInfo.cpp | 31 const RISCVSubtarget *STI) { in RISCVMachineFunctionInfo()
100 if (MF.getSubtarget<RISCVSubtarget>().hasStdExtZcmp() && in getPushPopKind()
106 if (MF.getSubtarget<RISCVSubtarget>().hasVendorXqccmp()) in getPushPopKind()
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| H A D | RISCVFrameLowering.h | 20 class RISCVSubtarget; variable
24 explicit RISCVFrameLowering(const RISCVSubtarget &STI);
88 const RISCVSubtarget &STI;
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| H A D | RISCVMacroFusion.cpp | |
| H A D | RISCVSubtarget.h | 79 class RISCVSubtarget : public RISCVGenSubtargetInfo {
120 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
128 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
132 ~RISCVSubtarget() override;
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| H A D | RISCVZacasABIFix.cpp | 35 const RISCVSubtarget *ST;
73 ST = &TM.getSubtarget<RISCVSubtarget>(F); in runOnFunction()
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| H A D | RISCVExpandAtomicPseudoInsts.cpp | 33 const RISCVSubtarget *STI;
74 STI = &MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
152 const RISCVSubtarget *Subtarget) { in getLRForRMW32()
174 const RISCVSubtarget *Subtarget) { in getSCForRMW32()
196 const RISCVSubtarget *Subtarget) { in getLRForRMW64()
218 const RISCVSubtarget *Subtarget) { in getSCForRMW64()
240 const RISCVSubtarget *Subtarget) { in getLRForRMW()
249 const RISCVSubtarget *Subtarget) { in getSCForRMW()
262 const RISCVSubtarget *STI) { in doAtomicBinOpExpansion()
326 const RISCVSubtarget *STI) { in doMaskedAtomicBinOpExpansion()
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| H A D | RISCVRegisterInfo.cpp | 68 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>(); in getCalleeSavedRegs()
126 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in getReservedRegs()
206 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in adjustReg()
399 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>(); in lowerVSPILL()
482 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>(); in lowerVRELOAD()
701 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in needsFrameBaseReg()
813 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in getCallPreservedMask()
892 return MF.getSubtarget<RISCVSubtarget>().hasStdExtZca() && !DisableCostPerUse in getRegisterCostTableIndex()
909 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in getRegAllocationHints()
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| H A D | RISCV.h | 25 class RISCVSubtarget; variable
101 const RISCVSubtarget &,
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| H A D | RISCVInsertWriteVXRM.cpp | 303 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in computeAnticipated()
442 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVVMV0Elimination.cpp | 82 const RISCVSubtarget *ST = &MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVTargetMachine.cpp | 202 const RISCVSubtarget *
273 I = std::make_unique<RISCVSubtarget>( in getSubtargetImpl()
283 Allocator, F, static_cast<const RISCVSubtarget *>(STI)); in createMachineFunctionInfo()
310 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>(); in createMachineScheduler()
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| H A D | RISCVPushPopOptimizer.cpp | 137 const RISCVSubtarget *Subtarget = &Fn.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVInsertReadWriteCSR.cpp | 177 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVMachineFunctionInfo.h | 90 RISCVMachineFunctionInfo(const Function &F, const RISCVSubtarget *STI);
128 MF.getSubtarget<RISCVSubtarget>().enableSaveRestore() &&
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVO0PreLegalizerCombiner.cpp | 43 const RISCVSubtarget &STI;
50 const RISCVSubtarget &STI);
70 const RISCVSubtarget &STI) in RISCVO0PreLegalizerCombinerImpl()
126 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVPostLegalizerCombiner.cpp | 49 const RISCVSubtarget &STI;
56 const RISCVSubtarget &STI, MachineDominatorTree *MDT,
77 const RISCVSubtarget &STI, MachineDominatorTree *MDT, in RISCVPostLegalizerCombinerImpl()
134 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVPreLegalizerCombiner.cpp | 45 const RISCVSubtarget &STI;
52 const RISCVSubtarget &STI, MachineDominatorTree *MDT,
73 const RISCVSubtarget &STI, MachineDominatorTree *MDT, in RISCVPreLegalizerCombinerImpl()
133 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVCallLowering.cpp | 61 Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {} in RISCVOutgoingValueHandler()
172 const RISCVSubtarget &Subtarget;
211 Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {} in RISCVIncomingValueHandler()
296 const RISCVSubtarget &Subtarget;
328 const RISCVSubtarget &Subtarget) { in isLegalElementTypeForRVV()
349 static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget, in isSupportedArgumentType()
371 static bool isSupportedReturnType(Type *T, const RISCVSubtarget &Subtarget, in isSupportedReturnType()
404 const RISCVSubtarget &Subtarget = in lowerReturn()
405 MIRBuilder.getMF().getSubtarget<RISCVSubtarget>(); in lowerReturn()
442 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in canLowerReturn()
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| H A D | RISCVLegalizerInfo.h | 24 class RISCVSubtarget; variable
27 const RISCVSubtarget &STI;
32 RISCVLegalizerInfo(const RISCVSubtarget &ST);
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| H A D | RISCVRegisterBankInfo.cpp | 329 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD()); in getInstrMapping()
363 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD()); in getInstrMapping()
470 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD()); in getInstrMapping()
481 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD()); in getInstrMapping()
497 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD()); in getInstrMapping()
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