| /freebsd/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | SparseBitVector.h | 239 // RHS1 & ~RHS2 into this element
240 void intersectWithComplement(const SparseBitVectorElement &RHS1, in intersectWithComplement()
247 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i]; in intersectWithComplement()
687 // Result of RHS1 & ~RHS2 is stored into this bitmap.
688 void intersectWithComplement(const SparseBitVector<ElementSize> &RHS1, in intersectWithComplement() argument
691 if (this == &RHS1) { in intersectWithComplement()
696 intersectWithComplement(RHS1, RHS2Copy); in intersectWithComplement()
702 ElementListConstIter Iter1 = RHS1.Elements.begin(); in intersectWithComplement()
705 // If RHS1 is empty, we are done in intersectWithComplement()
706 // If RHS2 is empty, we still have to copy RHS1 in intersectWithComplement()
734 intersectWithComplement(const SparseBitVector<ElementSize> * RHS1,const SparseBitVector<ElementSize> * RHS2) intersectWithComplement() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1410 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in matchIsFiniteTest() local
1414 !matchUnorderedInfCompare(PredR, RHS0, RHS1)) in matchIsFiniteTest()
1417 return Builder.CreateFCmpFMF(FCmpInst::getOrderedPredicate(PredR), RHS0, RHS1, in matchIsFiniteTest()
1424 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in foldLogicOfFCmps() local
1427 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1430 std::swap(RHS0, RHS1); in foldLogicOfFCmps()
1447 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
1468 if (match(LHS1, m_PosZeroFP()) && match(RHS1, m_PosZeroFP())) { in foldLogicOfFCmps()
1495 fcmpToClassTest(PredR, *RHS->getFunction(), RHS0, RHS1); in foldLogicOfFCmps()
1519 match(RHS1, m_APFloatAllowPoison(RHSC)) && in foldLogicOfFCmps()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | GuardWidening.cpp | 728 ConstantInt *RHS0, *RHS1; in mergeChecks() local
737 m_ICmp(Pred1, m_Specific(LHS), m_ConstantInt(RHS1)))) { in mergeChecks()
742 ConstantRange::makeExactICmpRegion(Pred1, RHS1->getValue()); in mergeChecks()
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| H A D | LICM.cpp | 2454 Value *LHS1, *LHS2, *RHS1, *RHS2; in hoistMinMax() local
2455 if (!MatchICmpAgainstInvariant(Cond1, P1, LHS1, RHS1) || in hoistMinMax()
2481 id, RHS1, RHS2, nullptr, in hoistMinMax()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 773 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, in getAVRCmp() local
787 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); in getAVRCmp()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 9510 const Value *RHS1, *RHS2; in isImpliedCondition() local
9511 if (match(RHS, m_LogicalOr(m_Value(RHS1), m_Value(RHS2)))) { in isImpliedCondition()
9513 isImpliedCondition(LHS, RHS1, DL, LHSIsTrue, Depth + 1)) in isImpliedCondition()
9521 if (match(RHS, m_LogicalAnd(m_Value(RHS1), m_Value(RHS2)))) { in isImpliedCondition()
9523 isImpliedCondition(LHS, RHS1, DL, LHSIsTrue, Depth + 1)) in isImpliedCondition()
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| H A D | InstructionSimplify.cpp | 1818 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in simplifyAndOrOfFCmps() local
1831 if ((match(RHS0, AbsOrSelfLHS0) || match(RHS1, AbsOrSelfLHS0)) && in simplifyAndOrOfFCmps()
1847 match(RHS1, m_PosZeroFP())) in simplifyAndOrOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 7513 Register RHS1 = Cmp2->getRHSReg(); in tryFoldLogicOfFCmps() local
7515 if (LHS0 == RHS1 && LHS1 == RHS0) { in tryFoldLogicOfFCmps()
7518 std::swap(RHS0, RHS1); in tryFoldLogicOfFCmps()
7521 if (LHS0 == RHS0 && LHS1 == RHS1) { in tryFoldLogicOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6550 SDValue RHS1 = RHS->getOperand(1); in foldAndOrOfSETCC() local
6554 auto *RHS1C = isConstOrConstSplat(RHS1); in foldAndOrOfSETCC()
6592 Operand2 = RHS1; in foldAndOrOfSETCC()
6594 } else if (LHS1 == RHS1) { in foldAndOrOfSETCC()
6602 if (LHS0 == RHS1) { in foldAndOrOfSETCC()
6610 Operand2 = RHS1; in foldAndOrOfSETCC()
6646 if (LHS0 == LHS1 && RHS0 == RHS1 && CCL == CCR && in foldAndOrOfSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5777 SDValue RHS1, RHS2; in OptimizeVFPBrcond() local
5779 expandf64Toi32(RHS, DAG, RHS1, RHS2); in OptimizeVFPBrcond()
5784 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
12307 Register RHS1 = MI.getOperand(3).getReg(); in EmitInstrWithCustomInserter() local
12311 .addReg(RHS1) in EmitInstrWithCustomInserter()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23862 SDValue RHS1, RHS2; in splitVSETCC() local
23863 std::tie(RHS1, RHS2) = splitVector(RHS, DAG, dl); in splitVSETCC()
23869 DAG.getNode(ISD::SETCC, dl, LoVT, LHS1, RHS1, CC), in splitVSETCC()
50383 SDValue RHS1 = RHS.getOperand(1); in combineVectorHADDSUB() local
50385 (RHS0 == RHS1 || RHS0.isUndef() || RHS1.isUndef())) { in combineVectorHADDSUB()
50389 RHS0.isUndef() ? RHS1 : RHS0); in combineVectorHADDSUB()
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