| /freebsd/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | SparseBitVector.h | 239 // RHS1 & ~RHS2 into this element
240 void intersectWithComplement(const SparseBitVectorElement &RHS1, in intersectWithComplement()
247 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i]; in intersectWithComplement()
687 // Result of RHS1 & ~RHS2 is stored into this bitmap.
688 void intersectWithComplement(const SparseBitVector<ElementSize> &RHS1, in intersectWithComplement() argument
691 if (this == &RHS1) { in intersectWithComplement()
696 intersectWithComplement(RHS1, RHS2Copy); in intersectWithComplement()
702 ElementListConstIter Iter1 = RHS1.Elements.begin(); in intersectWithComplement()
705 // If RHS1 is empty, we are done in intersectWithComplement()
706 // If RHS2 is empty, we still have to copy RHS1 in intersectWithComplement()
734 intersectWithComplement(const SparseBitVector<ElementSize> * RHS1,const SparseBitVector<ElementSize> * RHS2) intersectWithComplement() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1362 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in matchIsFiniteTest() local
1366 !matchUnorderedInfCompare(PredR, RHS0, RHS1)) in matchIsFiniteTest()
1374 return Builder.CreateFCmp(FCmpInst::getOrderedPredicate(PredR), RHS0, RHS1); in matchIsFiniteTest()
1380 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in foldLogicOfFCmps() local
1383 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1386 std::swap(RHS0, RHS1); in foldLogicOfFCmps()
1403 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
1428 if (match(LHS1, m_PosZeroFP()) && match(RHS1, m_PosZeroFP())) in foldLogicOfFCmps()
1451 fcmpToClassTest(PredR, *RHS->getFunction(), RHS0, RHS1); in foldLogicOfFCmps()
1475 match(RHS1, m_APFloatAllowPoison(RHSC)) && in foldLogicOfFCmps()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | GuardWidening.cpp | 729 ConstantInt *RHS0, *RHS1; in mergeChecks() local
738 m_ICmp(Pred1, m_Specific(LHS), m_ConstantInt(RHS1)))) { in mergeChecks()
743 ConstantRange::makeExactICmpRegion(Pred1, RHS1->getValue()); in mergeChecks()
|
| H A D | LICM.cpp | 2443 Value *LHS1, *LHS2, *RHS1, *RHS2; in hoistMinMax() local
2444 if (!MatchICmpAgainstInvariant(Cond1, P1, LHS1, RHS1) || in hoistMinMax()
2468 id, RHS1, RHS2, nullptr, StringRef("invariant.") + in hoistMinMax()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 827 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, in getAVRCmp() local
841 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); in getAVRCmp()
|
| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 9239 const Value *RHS1, *RHS2; in isImpliedCondition() local
9240 if (match(RHS, m_LogicalOr(m_Value(RHS1), m_Value(RHS2)))) { in isImpliedCondition()
9242 isImpliedCondition(LHS, RHS1, DL, LHSIsTrue, Depth + 1)) in isImpliedCondition()
9250 if (match(RHS, m_LogicalAnd(m_Value(RHS1), m_Value(RHS2)))) { in isImpliedCondition()
9252 isImpliedCondition(LHS, RHS1, DL, LHSIsTrue, Depth + 1)) in isImpliedCondition()
|
| H A D | InstructionSimplify.cpp | 1867 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in simplifyAndOrOfFCmps() local
1879 if ((LHS0 == RHS0 || LHS0 == RHS1) && match(LHS1, m_PosZeroFP())) in simplifyAndOrOfFCmps()
1892 if ((RHS0 == LHS0 || RHS0 == LHS1) && match(RHS1, m_PosZeroFP())) in simplifyAndOrOfFCmps()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 7176 Register RHS1 = Cmp2->getRHSReg(); in tryFoldLogicOfFCmps() local
7178 if (LHS0 == RHS1 && LHS1 == RHS0) { in tryFoldLogicOfFCmps()
7181 std::swap(RHS0, RHS1); in tryFoldLogicOfFCmps()
7184 if (LHS0 == RHS0 && LHS1 == RHS1) { in tryFoldLogicOfFCmps()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5696 SDValue RHS1, RHS2; in OptimizeVFPBrcond() local
5698 expandf64Toi32(RHS, DAG, RHS1, RHS2); in OptimizeVFPBrcond()
5704 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
12244 Register RHS1 = MI.getOperand(3).getReg(); in EmitInstrWithCustomInserter() local
12248 .addReg(RHS1) in EmitInstrWithCustomInserter()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6171 SDValue RHS1 = RHS->getOperand(1); in foldAndOrOfSETCC() local
6175 auto *RHS1C = isConstOrConstSplat(RHS1); in foldAndOrOfSETCC()
6213 Operand2 = RHS1; in foldAndOrOfSETCC()
6215 } else if (LHS1 == RHS1) { in foldAndOrOfSETCC()
6223 if (LHS0 == RHS1) { in foldAndOrOfSETCC()
6231 Operand2 = RHS1; in foldAndOrOfSETCC()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23122 SDValue RHS1, RHS2; in splitIntVSETCC() local
23123 std::tie(RHS1, RHS2) = splitVector(RHS, DAG, dl); in splitIntVSETCC()
23129 DAG.getNode(ISD::SETCC, dl, LoVT, LHS1, RHS1, CC), in splitIntVSETCC()
48628 SDValue RHS1 = RHS.getOperand(1); in combineVectorHADDSUB() local
48630 (RHS0 == RHS1 || RHS0.isUndef() || RHS1.isUndef())) { in combineVectorHADDSUB()
48634 RHS0.isUndef() ? RHS1 : RHS0); in combineVectorHADDSUB()
|