Searched refs:RHS0 (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1410 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in matchIsFiniteTest() local
1414 !matchUnorderedInfCompare(PredR, RHS0, RHS1)) in matchIsFiniteTest()
1417 return Builder.CreateFCmpFMF(FCmpInst::getOrderedPredicate(PredR), RHS0, RHS1, in matchIsFiniteTest()
1424 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in foldLogicOfFCmps() local
1427 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1430 std::swap(RHS0, RHS1); in foldLogicOfFCmps()
1447 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
1463 if (LHS0->getType() != RHS0->getType()) in foldLogicOfFCmps()
1472 return Builder.CreateFCmpFMF(PredL, LHS0, RHS0, in foldLogicOfFCmps()
1479 stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) { in foldLogicOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | GuardWidening.cpp | 728 ConstantInt *RHS0, *RHS1; in mergeChecks() local
735 m_ICmp(Pred0, m_Value(LHS), m_ConstantInt(RHS0))) && in mergeChecks()
740 ConstantRange::makeExactICmpRegion(Pred0, RHS0->getValue()); in mergeChecks()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1818 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in simplifyAndOrOfFCmps() local
1819 if (LHS0->getType() != RHS0->getType()) in simplifyAndOrOfFCmps()
1831 if ((match(RHS0, AbsOrSelfLHS0) || match(RHS1, AbsOrSelfLHS0)) && in simplifyAndOrOfFCmps()
1838 auto AbsOrSelfRHS0 = m_CombineOr(m_Specific(RHS0), m_FAbs(m_Specific(RHS0))); in simplifyAndOrOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 771 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, in getAVRCmp() local
786 Cmp = getAVRCmp(LHS0, RHS0, DAG, DL); in getAVRCmp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 7512 Register RHS0 = Cmp2->getLHSReg(); in tryFoldLogicOfFCmps() local
7515 if (LHS0 == RHS1 && LHS1 == RHS0) { in tryFoldLogicOfFCmps()
7518 std::swap(RHS0, RHS1); in tryFoldLogicOfFCmps()
7521 if (LHS0 == RHS0 && LHS1 == RHS1) { in tryFoldLogicOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6548 SDValue RHS0 = RHS->getOperand(0); in foldAndOrOfSETCC() local
6589 if (LHS0 == RHS0) { in foldAndOrOfSETCC()
6597 Operand2 = RHS0; in foldAndOrOfSETCC()
6605 Operand2 = RHS0; in foldAndOrOfSETCC()
6607 } else if (RHS0 == LHS1) { in foldAndOrOfSETCC()
6646 if (LHS0 == LHS1 && RHS0 == RHS1 && CCL == CCR && in foldAndOrOfSETCC()
6647 LHS0.getValueType() == RHS0.getValueType() && in foldAndOrOfSETCC()
6650 return DAG.getSetCC(DL, VT, LHS0, RHS0, CCL); in foldAndOrOfSETCC()
6657 LHS0 == RHS0 && LHS1C && RHS1C && OpVT.isInteger()) { in foldAndOrOfSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 50382 SDValue RHS0 = RHS.getOperand(0); in combineVectorHADDSUB() local
50385 (RHS0 == RHS1 || RHS0.isUndef() || RHS1.isUndef())) { in combineVectorHADDSUB()
50389 RHS0.isUndef() ? RHS1 : RHS0); in combineVectorHADDSUB()
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