Searched refs:RHS0 (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1362 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in matchIsFiniteTest() local
1366 !matchUnorderedInfCompare(PredR, RHS0, RHS1)) in matchIsFiniteTest()
1374 return Builder.CreateFCmp(FCmpInst::getOrderedPredicate(PredR), RHS0, RHS1); in matchIsFiniteTest()
1380 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in foldLogicOfFCmps() local
1383 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1386 std::swap(RHS0, RHS1); in foldLogicOfFCmps()
1403 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
1423 if (LHS0->getType() != RHS0->getType()) in foldLogicOfFCmps()
1432 return Builder.CreateFCmp(PredL, LHS0, RHS0); in foldLogicOfFCmps()
1435 if (IsAnd && stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) { in foldLogicOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | GuardWidening.cpp | 729 ConstantInt *RHS0, *RHS1; in mergeChecks() local
736 m_ICmp(Pred0, m_Value(LHS), m_ConstantInt(RHS0))) && in mergeChecks()
741 ConstantRange::makeExactICmpRegion(Pred0, RHS0->getValue()); in mergeChecks()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1867 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in simplifyAndOrOfFCmps() local
1868 if (LHS0->getType() != RHS0->getType()) in simplifyAndOrOfFCmps()
1879 if ((LHS0 == RHS0 || LHS0 == RHS1) && match(LHS1, m_PosZeroFP())) in simplifyAndOrOfFCmps()
1892 if ((RHS0 == LHS0 || RHS0 == LHS1) && match(RHS1, m_PosZeroFP())) in simplifyAndOrOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 825 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, in getAVRCmp() local
840 Cmp = getAVRCmp(LHS0, RHS0, DAG, DL); in getAVRCmp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 7175 Register RHS0 = Cmp2->getLHSReg(); in tryFoldLogicOfFCmps() local
7178 if (LHS0 == RHS1 && LHS1 == RHS0) { in tryFoldLogicOfFCmps()
7181 std::swap(RHS0, RHS1); in tryFoldLogicOfFCmps()
7184 if (LHS0 == RHS0 && LHS1 == RHS1) { in tryFoldLogicOfFCmps()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6169 SDValue RHS0 = RHS->getOperand(0); in foldAndOrOfSETCC() local
6210 if (LHS0 == RHS0) { in foldAndOrOfSETCC()
6218 Operand2 = RHS0; in foldAndOrOfSETCC()
6226 Operand2 = RHS0; in foldAndOrOfSETCC()
6228 } else if (RHS0 == LHS1) { in foldAndOrOfSETCC()
6272 LHS0 == RHS0 && LHS1C && RHS1C && OpVT.isInteger()) { in foldAndOrOfSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 48627 SDValue RHS0 = RHS.getOperand(0); in combineVectorHADDSUB() local
48630 (RHS0 == RHS1 || RHS0.isUndef() || RHS1.isUndef())) { in combineVectorHADDSUB()
48634 RHS0.isUndef() ? RHS1 : RHS0); in combineVectorHADDSUB()
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