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Searched refs:RGMII (Results 1 – 25 of 50) sorted by relevance

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/freebsd/sys/contrib/device-tree/include/dt-bindings/phy/
H A Dphy-lan966x-serdes.h10 #define RGMII(x) (SERDES6G_MAX + 1 + (x)) macro
11 #define RGMII_MAX RGMII(2)
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dxilinx_gmii2rgmii.txt5 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
H A Dmediatek-dwmac.txt25 It should be defined for RGMII/MII interface.
28 It should be defined for RGMII/MII interface.
30 Both delay properties need to be a multiple of 170 for RGMII interface,
42 1. tx clock will be inversed in MII/RGMII case,
48 1. rx clock will be inversed in MII/RGMII case.
H A Dibm,emac.txt5 special McMAL DMA controller, and sometimes an RGMII or ZMII
55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
56 of the RGMII device node.
58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
59 RGMII channel is used by this EMAC.
195 iv) RGMII node
203 - revision : as provided by the RGMII new version register if
H A Dapm-xgene-enet.txt8 - "apm,xgene-enet": RGMII based 1G interface
42 - tx-delay: Delay value for RGMII bridge TX clock.
46 - rx-delay: Delay value for RGMII bridge RX clock.
H A Dcavium-pip.txt40 - rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0.
43 - tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0.
H A Dbrcm,bcmgenet.txt29 when operating in a RGMII to RGMII type of connection, or when the MDIO bus is
H A Dimx-dwmac.txt15 Should be "tx" for the MAC RGMII TX clock:
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dsja1105.txt19 of support for RGMII internal delays (supported on P/Q/R/S, but not on
33 clock source or sink for this interface (not applicable for RGMII
35 - In the case of RGMII it affects the behavior regarding internal
39 designated to apply the delay/clock skew necessary for RGMII
45 E or T device, it is an error to specify an RGMII phy-mode other
H A Dmt7530.txt54 In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
58 and RGMII delay.
68 2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti-phy-gmii-sel.txt5 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
26 | | | RGMII <------->
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dkmeter1.dts314 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
330 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
457 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
464 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
H A Dfsp2.dts538 rgmii-device = <&RGMII>;
564 rgmii-device = <&RGMII>;
568 RGMII: rgmii@b0000600 { label
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-lx2160a-bluebox3-rev-a.dts15 /* The RGMII PHYs have a different MDIO address */
H A Dfsl-ls1028a-kontron-sl28-var4.dts6 * extends the base and provides one more port connected via RGMII.
H A Dfsl-ls1028a-kontron-sl28-var1.dts7 * port is connected via RGMII. This port is not TSN aware.
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxm-vega-s96.dts28 /* External PHY is in RGMII */
H A Dmeson-gxm-q200.dts53 /* External PHY is in RGMII */
H A Dmeson-gxl-s905d-p230.dts71 /* External PHY is in RGMII */
H A Dmeson-gxbb-odroidc2.dts294 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
296 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
H A Dmeson-gxbb-nanopi-k2.dts251 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
253 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7100-starfive-visionfive-v1.dts26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-sama5d3_eds.dts211 /* Reserved for reset signal to the RGMII connector. */
217 /* Reserved for an interrupt line from the RMII and RGMII connectors. */
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qp-prtwd3.dts460 /* Configure clock provider for RGMII ref clock */
462 /* Configure clock consumer for RGMII ref clock */
H A Dimx6qdl-wandboard-revd1.dtsi147 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */

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