Searched refs:REF_CLK (Results 1 – 7 of 7) sorted by relevance
7 - clocks: common clock binding for CLK_IN, XTI/REF_CLK8 - clock-names: CLK_IN : clk_in, XTI/REF_CLK : ref_clk
17 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
37 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
44 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
533 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */573 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
115 #define REF_CLK 106 macro
154 * REF_CLK from the PHY is fed back into the i.MX6 and the GPR