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Searched refs:RCOrRB (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp396 if (const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg)) { in addNodeIDReg()
397 if (const auto *RB = dyn_cast_if_present<const RegisterBank *>(RCOrRB)) in addNodeIDReg()
400 dyn_cast_if_present<const TargetRegisterClass *>(RCOrRB)) in addNodeIDReg()
398 if (const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg)) { addNodeIDReg() local
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h698 const RegClassOrRegBank &RCOrRB){ in setRegClassOrRegBank() argument
699 VRegInfo[Reg].first = RCOrRB; in setRegClassOrRegBank()
748 RegClassOrRegBank RCOrRB; member
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp244 dyn_cast_or_null<const TargetRegisterClass *>(RegAttrs.RCOrRB); in RewriteUse()
H A DMachineRegisterInfo.cpp175 VRegInfo[Reg].first = RegAttr.RCOrRB; in createVirtualRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp3116 const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg()); in getConstrainedRegClassForOperand() local
3117 if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>()) in getConstrainedRegClassForOperand()
3120 if (const auto *RC = RCOrRB.dyn_cast<const TargetRegisterClass *>()) in getConstrainedRegClassForOperand()