| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterClassInfo.cpp | 127 RCInfo &RCI = RegClass[RC->getID()]; in compute() local
133 if (!RCI.Order) in compute()
134 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
159 RCI.Order[N++] = PhysReg; in compute()
163 RCI.NumRegs = N + CSRAlias.size(); in compute()
164 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
171 RCI.Order[N++] = PhysReg; in compute()
176 if (StressRA && RCI.NumRegs > StressRA) in compute()
177 RCI.NumRegs = StressRA; in compute()
182 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
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| H A D | TargetRegisterInfo.cpp | 307 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) in getMatchingSuperRegClass() local
308 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
311 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); in getMatchingSuperRegClass()
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| H A D | CriticalAntiDepBreaker.cpp | 42 const RegisterClassInfo &RCI) in CriticalAntiDepBreaker() argument
44 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
696 const RegisterClassInfo &RCI) { in createCriticalAntiDepBreaker() argument
697 return new CriticalAntiDepBreaker(MFi, RCI); in createCriticalAntiDepBreaker()
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| H A D | CriticalAntiDepBreaker.h | 74 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI);
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| H A D | PostRASchedulerList.cpp | 204 const RegisterClassInfo &RCI, in SchedulePostRATDList() argument
220 ? createAggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) in SchedulePostRATDList()
222 ? createCriticalAntiDepBreaker(MF, RCI) in SchedulePostRATDList()
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| H A D | AggressiveAntiDepBreaker.h | 133 const RegisterClassInfo &RCI,
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| H A D | AggressiveAntiDepBreaker.cpp | 121 MachineFunction &MFi, const RegisterClassInfo &RCI, in AggressiveAntiDepBreaker() argument
124 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) { in AggressiveAntiDepBreaker()
964 MachineFunction &MFi, const RegisterClassInfo &RCI, in createAggressiveAntiDepBreaker() argument
966 return new AggressiveAntiDepBreaker(MFi, RCI, CriticalPathRCs); in createAggressiveAntiDepBreaker()
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| H A D | RegisterPressure.cpp | 273 RCI = rci; in init()
954 const RegisterClassInfo *RCI, in computeExcessPressureDelta() argument
964 unsigned Limit = RCI->getRegPressureSetLimit(i); in computeExcessPressureDelta()
1107 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI, in getMaxUpwardPressureDelta()
1173 unsigned Limit = RCI->getRegPressureSetLimit(PSetID); in getUpwardPressureDelta()
1353 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI, in getMaxDownwardPressureDelta()
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| H A D | ShrinkWrap.cpp | 116 RegisterClassInfo RCI; member in __anon8a4a73dd0111::ShrinkWrap
227 RCI.runOnMachineFunction(MF); in init()
354 RCI.getLastCalleeSavedAlias(PhysReg) || in INITIALIZE_PASS_DEPENDENCY()
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| H A D | TargetLoweringBase.cpp | 1232 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) in findRepresentativeClass() local
1233 SuperRegRC.setBitsInMask(RCI.getMask()); in findRepresentativeClass()
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| H A D | RegAllocGreedy.cpp | 1339 const RegisterClassInfo &RCI) { in getNumAllocatableRegsForConstraints() argument
1347 return RCI.getNumAllocatableRegs(ConstrainedRC); in getNumAllocatableRegsForConstraints()
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| H A D | MachinePipeliner.cpp | 1330 void computePressureSetLimit(const RegisterClassInfo &RCI) { in computePressureSetLimit() argument
1540 void init(const RegisterClassInfo &RCI) { in init() argument
1548 computePressureSetLimit(RCI); in init()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 79 const RCInfo &RCI = RegClass[RC->getID()]; in get() local
80 if (Tag != RCI.Tag) in get()
82 return RCI; in get()
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| H A D | AntiDepBreaker.h | 94 MachineFunction &MFi, const RegisterClassInfo &RCI,
98 const RegisterClassInfo &RCI);
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| H A D | RegisterPressure.h | 362 const RegisterClassInfo *RCI = nullptr; variable
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 192 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) { in getSuperRegClassMask() local
193 if (RCI.getSubReg() == SubRegIdx) { in getSuperRegClassMask()
194 I->second = RCI.getMask(); in getSuperRegClassMask()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | ConstantHoisting.cpp | 167 for (const RebasedConstantInfo &RCI : RebasedConstants) in collectMatInsertPts() local
168 for (const ConstantUser &U : RCI.Uses) in collectMatInsertPts()
869 for (auto const &RCI : ConstInfo.RebasedConstants) { in emitBaseConstants() local
870 UsesNum += RCI.Uses.size(); in emitBaseConstants()
871 for (auto const &U : RCI.Uses) { in emitBaseConstants()
878 ToBeRebased.emplace_back(RCI.Offset, RCI.Ty, MatInsertPt, U); in emitBaseConstants()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 111 RegisterClassInfo RCI;
320 RCI.runOnMachineFunction(F); in runOnMachineFunction()
518 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
112 RegisterClassInfo RCI; global() member in __anon820378290111::AArch64A57FPLoadBalancing
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