Searched refs:RC0 (Results 1 – 6 of 6) sorted by relevance
223 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction() local224 if (RC0->getID() == Hexagon::PredRegsRegClassID) { in runOnMachineFunction()
835 const TargetRegisterClass *RC0 = MRI->getRegClass(PHIRes); in processPHINode() local836 if (HasUses && AllAGPRUses && !TRI->isAGPRClass(RC0)) { in processPHINode()838 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()847 RC0 == &AMDGPU::VReg_1RegClass) { in processPHINode()
1406 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in findAndSortDefOperandIndexes() local1411 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in findAndSortDefOperandIndexes()1414 bool SmallClass0 = ClassSize0 < RegClassDefCounts[RC0.getID()]; in findAndSortDefOperandIndexes()
1140 volatile u_int32_t RC0[118]; /* 0x1000 - 0x11d8 */ member
2535 #define AR_RC0_0 AR_SVD_OFFSET(RC0)
1905 volatile u_int32_t RC0[118]; /* 0x11000 - 0x111d8 */ member