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Searched refs:RBX (Results 1 – 16 of 16) sorted by relevance

/freebsd/lib/libc/amd64/string/
H A Dstrncmp.S248 lea (%rsi, %rax, 1), %rbx # point RBX to offset in second string
337 shl %cl, %r8d # adjust NUL mask to positions in RDI/RBX
367 add %rdi, %rbx # turn RBX from offset into pointer
379 lea (%rdi, %rax, 1), %rbx # point RBX to offset in first string
456 shl %cl, %r8d # adjust NUL mask to positions in RSI/RBX
480 add %rsi, %rbx # turn RBX from offset into pointer
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td697 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
1040 // - RBX base pointer
1121 def CSR_IPRA_64 : CalleeSavedRegs<(add RBP, RBX)>;
1124 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1132 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1165 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
1180 def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9,
1192 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
1196 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
1208 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RSI, R14, R15,
[all …]
H A DX86ExpandPseudo.cpp442 TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, InArg.getReg(), false); in expandMI()
448 if (Base.getReg() == X86::RBX || Base.getReg() == X86::EBX) in expandMI()
450 Base.getReg() == X86::RBX in expandMI()
459 TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx, in expandMI()
561 TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx, /*SrcIsKill*/ true); in expandMI()
H A DX86InstrSystem.td452 let Defs = [RAX, EFLAGS], Uses = [RBX, RCX], Predicates = [In64BitMode] in
672 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
774 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
844 // RBX/RCX/RDX: Leaf-specific purpose."
851 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
H A DX86RegisterInfo.td286 def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>;
540 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
593 R18, R19, R22, R23, R24, R25, R26, R27, R30, R31, RBX,
600 RBX, R14, R15, R12, R13, RBP)>;
635 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
659 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
H A DX86InstrCompiler.td970 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
978 // This pseudo must be used when the frame uses RBX as
979 // the base pointer. Indeed, in such situation RBX is a reserved
982 // RBX that will happen when setting the arguments for the instrucion.
985 // defines RBX (instead of using RBX).
986 // The rationale is that we will define RBX during the expansion of
987 // the pseudo. The argument feeding RBX is rbx_input.
990 // save the value of RBX across the actual instruction.
996 // the value of RBX.
997 let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX],
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H A DX86RegisterInfo.cpp78 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; in X86RegisterInfo()
H A DX86FrameLowering.cpp4459 MI->getOperand(1).getReg() == X86::RBX) && in skipSpillFPBP()
4460 !((Reg = TII.isStoreToStackSlot(*MI, FI)) && Reg == X86::RBX)) in skipSpillFPBP()
H A DX86InstrMisc.td954 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
H A DX86ISelLowering.cpp38026 (BasePtr == X86::RBX || BasePtr == X86::EBX)) { in EmitInstrWithCustomInserter()
38033 .addReg(X86::RBX); in EmitInstrWithCustomInserter()
38043 BuildMI(*BB, MI, MIMD, TII->get(TargetOpcode::COPY), X86::RBX) in EmitInstrWithCustomInserter()
38056 bool IsRBX = (BasePtr == X86::RBX || BasePtr == X86::EBX); in EmitInstrWithCustomInserter()
38082 .addReg(X86::RBX); in EmitInstrWithCustomInserter()
61950 case X86::RBX: in getRegForInlineAsmConstraint()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp257 {codeview::RegisterId::RBX, X86::RBX}, in initLLVMToSEHAndCVRegMapping()
782 SUB_SUPER(BL, BX, EBX, RBX, R) in getX86SubSuperRegister()
920 B_SUB_SUPER(RBX) in getX86SubSuperRegister()
H A DX86AsmBackend.cpp1191 case X86::RBX: in PushInstrSize()
1211 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCompactUnwindRegNum()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h291 ENTRY(RBX) \
325 ENTRY(RBX) \
/freebsd/sys/amd64/amd64/
H A Dbpf_jit_machdep.h43 #define RBX 3 macro
/freebsd/contrib/llvm-project/lldb/source/Plugins/SymbolFile/NativePDB/
H A DCodeViewRegisterMapping.cpp712 case llvm::codeview::RegisterId::RBX: in GetRegisterSize()
/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def222 CV_REGISTER(RBX, 329)