Searched refs:RBGPR (Results 1 – 4 of 4) sorted by relevance
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo() local143 (void)RBGPR; in ARMRegisterBankInfo()144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()[all …]
35 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo() local36 (void)RBGPR; in X86RegisterBankInfo()37 assert(&X86::GPRRegBank == &RBGPR && "Incorrect RegBanks inizalization."); in X86RegisterBankInfo()41 assert(RBGPR.covers(*TRI.getRegClass(X86::GR64RegClassID)) && in X86RegisterBankInfo()43 assert(getMaximumSize(RBGPR.getID()) == 64 && in X86RegisterBankInfo()
57 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo() local58 (void)RBGPR; in AArch64RegisterBankInfo()59 assert(&AArch64::GPRRegBank == &RBGPR && in AArch64RegisterBankInfo()74 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()76 assert(getMaximumSize(RBGPR.getID()) == 128 && in AArch64RegisterBankInfo()111 CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR); in AArch64RegisterBankInfo()112 CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR); in AArch64RegisterBankInfo()113 CHECK_PARTIALMAP(PMI_GPR128, 0, 128, RBGPR); in AArch64RegisterBankInfo()