1 2 /*- 3 * Copyright (c) 2005, 2006 4 * Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #define RAL_NOISE_FLOOR -95 20 #define RAL_RSSI_CORR 120 21 22 #define RAL_RX_DESC_SIZE (sizeof (struct ural_rx_desc)) 23 #define RAL_TX_DESC_SIZE (sizeof (struct ural_tx_desc)) 24 #define RAL_FRAME_SIZE 0x780 /* NOTE: using 0x980 does not work */ 25 26 #define RAL_CONFIG_NO 1 27 #define RAL_IFACE_INDEX 0 28 29 #define RAL_VENDOR_REQUEST 0x01 30 #define RAL_WRITE_MAC 0x02 31 #define RAL_READ_MAC 0x03 32 #define RAL_WRITE_MULTI_MAC 0x06 33 #define RAL_READ_MULTI_MAC 0x07 34 #define RAL_READ_EEPROM 0x09 35 36 /* 37 * MAC registers. 38 */ 39 #define RAL_MAC_CSR0 0x0400 /* ASIC Version */ 40 #define RAL_MAC_CSR1 0x0402 /* System control */ 41 #define RAL_MAC_CSR2 0x0404 /* MAC addr0 */ 42 #define RAL_MAC_CSR3 0x0406 /* MAC addr1 */ 43 #define RAL_MAC_CSR4 0x0408 /* MAC addr2 */ 44 #define RAL_MAC_CSR5 0x040a /* BSSID0 */ 45 #define RAL_MAC_CSR6 0x040c /* BSSID1 */ 46 #define RAL_MAC_CSR7 0x040e /* BSSID2 */ 47 #define RAL_MAC_CSR8 0x0410 /* Max frame length */ 48 #define RAL_MAC_CSR9 0x0412 /* Timer control */ 49 #define RAL_MAC_CSR10 0x0414 /* Slot time */ 50 #define RAL_MAC_CSR11 0x0416 /* IFS */ 51 #define RAL_MAC_CSR12 0x0418 /* EIFS */ 52 #define RAL_MAC_CSR13 0x041a /* Power mode0 */ 53 #define RAL_MAC_CSR14 0x041c /* Power mode1 */ 54 #define RAL_MAC_CSR15 0x041e /* Power saving transition0 */ 55 #define RAL_MAC_CSR16 0x0420 /* Power saving transition1 */ 56 #define RAL_MAC_CSR17 0x0422 /* Power state control */ 57 #define RAL_MAC_CSR18 0x0424 /* Auto wake-up control */ 58 #define RAL_MAC_CSR19 0x0426 /* GPIO control */ 59 #define RAL_MAC_CSR20 0x0428 /* LED control0 */ 60 #define RAL_MAC_CSR22 0x042c /* XXX not documented */ 61 62 /* 63 * Tx/Rx Registers. 64 */ 65 #define RAL_TXRX_CSR0 0x0440 /* Security control */ 66 #define RAL_TXRX_CSR2 0x0444 /* Rx control */ 67 #define RAL_TXRX_CSR5 0x044a /* CCK Tx BBP ID0 */ 68 #define RAL_TXRX_CSR6 0x044c /* CCK Tx BBP ID1 */ 69 #define RAL_TXRX_CSR7 0x044e /* OFDM Tx BBP ID0 */ 70 #define RAL_TXRX_CSR8 0x0450 /* OFDM Tx BBP ID1 */ 71 #define RAL_TXRX_CSR10 0x0454 /* Auto responder control */ 72 #define RAL_TXRX_CSR11 0x0456 /* Auto responder basic rate */ 73 #define RAL_TXRX_CSR18 0x0464 /* Beacon interval */ 74 #define RAL_TXRX_CSR19 0x0466 /* Beacon/sync control */ 75 #define RAL_TXRX_CSR20 0x0468 /* Beacon alignment */ 76 #define RAL_TXRX_CSR21 0x046a /* XXX not documented */ 77 78 /* 79 * Security registers. 80 */ 81 #define RAL_SEC_CSR0 0x0480 /* Shared key 0, word 0 */ 82 83 /* 84 * PHY registers. 85 */ 86 #define RAL_PHY_CSR2 0x04c4 /* Tx MAC configuration */ 87 #define RAL_PHY_CSR4 0x04c8 /* Interface configuration */ 88 #define RAL_PHY_CSR5 0x04ca /* BBP Pre-Tx CCK */ 89 #define RAL_PHY_CSR6 0x04cc /* BBP Pre-Tx OFDM */ 90 #define RAL_PHY_CSR7 0x04ce /* BBP serial control */ 91 #define RAL_PHY_CSR8 0x04d0 /* BBP serial status */ 92 #define RAL_PHY_CSR9 0x04d2 /* RF serial control0 */ 93 #define RAL_PHY_CSR10 0x04d4 /* RF serial control1 */ 94 95 /* 96 * Statistics registers. 97 */ 98 #define RAL_STA_CSR0 0x04e0 /* FCS error */ 99 100 #define RAL_DISABLE_RX (1 << 0) 101 #define RAL_DROP_CRC (1 << 1) 102 #define RAL_DROP_PHY (1 << 2) 103 #define RAL_DROP_CTL (1 << 3) 104 #define RAL_DROP_NOT_TO_ME (1 << 4) 105 #define RAL_DROP_TODS (1 << 5) 106 #define RAL_DROP_BAD_VERSION (1 << 6) 107 #define RAL_DROP_MULTICAST (1 << 9) 108 #define RAL_DROP_BROADCAST (1 << 10) 109 110 #define RAL_SHORT_PREAMBLE (1 << 2) 111 112 #define RAL_RESET_ASIC (1 << 0) 113 #define RAL_RESET_BBP (1 << 1) 114 #define RAL_HOST_READY (1 << 2) 115 116 #define RAL_ENABLE_TSF (1 << 0) 117 #define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) 118 #define RAL_ENABLE_TBCN (1 << 3) 119 #define RAL_ENABLE_BEACON_GENERATOR (1 << 4) 120 121 #define RAL_RF_AWAKE (3 << 7) 122 #define RAL_BBP_AWAKE (3 << 5) 123 124 #define RAL_BBP_WRITE (1 << 15) 125 #define RAL_BBP_BUSY (1 << 0) 126 127 #define RAL_RF1_AUTOTUNE 0x08000 128 #define RAL_RF3_AUTOTUNE 0x00040 129 130 #define RAL_RF_2522 0x00 131 #define RAL_RF_2523 0x01 132 #define RAL_RF_2524 0x02 133 #define RAL_RF_2525 0x03 134 #define RAL_RF_2525E 0x04 135 #define RAL_RF_2526 0x05 136 /* dual-band RF */ 137 #define RAL_RF_5222 0x10 138 139 #define RAL_BBP_VERSION 0 140 #define RAL_BBP_TX 2 141 #define RAL_BBP_RX 14 142 143 #define RAL_BBP_ANTA 0x00 144 #define RAL_BBP_DIVERSITY 0x01 145 #define RAL_BBP_ANTB 0x02 146 #define RAL_BBP_ANTMASK 0x03 147 #define RAL_BBP_FLIPIQ 0x04 148 149 #define RAL_JAPAN_FILTER 0x08 150 151 struct ural_tx_desc { 152 uint32_t flags; 153 #define RAL_TX_RETRY(x) ((x) << 4) 154 #define RAL_TX_MORE_FRAG (1 << 8) 155 #define RAL_TX_ACK (1 << 9) 156 #define RAL_TX_TIMESTAMP (1 << 10) 157 #define RAL_TX_OFDM (1 << 11) 158 #define RAL_TX_NEWSEQ (1 << 12) 159 160 #define RAL_TX_IFS_MASK 0x00006000 161 #define RAL_TX_IFS_BACKOFF (0 << 13) 162 #define RAL_TX_IFS_SIFS (1 << 13) 163 #define RAL_TX_IFS_NEWBACKOFF (2 << 13) 164 #define RAL_TX_IFS_NONE (3 << 13) 165 166 uint16_t wme; 167 #define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) 168 #define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) 169 #define RAL_AIFSN(x) (((x) & 0x3) << 6) 170 #define RAL_IVOFFSET(x) (((x) & 0x3f)) 171 172 uint16_t reserved1; 173 uint8_t plcp_signal; 174 uint8_t plcp_service; 175 #define RAL_PLCP_LENGEXT 0x80 176 177 uint8_t plcp_length_lo; 178 uint8_t plcp_length_hi; 179 uint32_t iv; 180 uint32_t eiv; 181 } __packed; 182 183 struct ural_rx_desc { 184 uint32_t flags; 185 #define RAL_RX_CRC_ERROR (1 << 5) 186 #define RAL_RX_OFDM (1 << 6) 187 #define RAL_RX_PHY_ERROR (1 << 7) 188 189 uint8_t rssi; 190 uint8_t rate; 191 uint16_t reserved; 192 193 uint32_t iv; 194 uint32_t eiv; 195 } __packed; 196 197 #define RAL_RF_LOBUSY (1 << 15) 198 #define RAL_RF_BUSY (1U << 31) 199 #define RAL_RF_20BIT (20 << 24) 200 201 #define RAL_RF1 0 202 #define RAL_RF2 2 203 #define RAL_RF3 1 204 #define RAL_RF4 3 205 206 #define RAL_EEPROM_ADDRESS 0x0004 207 #define RAL_EEPROM_TXPOWER 0x003c 208 #define RAL_EEPROM_CONFIG0 0x0016 209 #define RAL_EEPROM_BBP_BASE 0x001c 210