Searched refs:R9A07G044_CLK_P0_DIV2 (Results 1 – 2 of 2) sorted by relevance
33 #define R9A07G044_CLK_P0_DIV2 22 macro
515 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,518 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;