1 /*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ 18 */ 19 20 #ifndef R92C_RX_DESC_H 21 #define R92C_RX_DESC_H 22 23 /* Rx MAC descriptor (common parts / USB). */ 24 struct r92c_rx_stat { 25 uint32_t rxdw0; 26 #define R92C_RXDW0_PKTLEN_M 0x00003fff 27 #define R92C_RXDW0_PKTLEN_S 0 28 #define R92C_RXDW0_CRCERR 0x00004000 29 #define R92C_RXDW0_ICVERR 0x00008000 30 #define R92C_RXDW0_INFOSZ_M 0x000f0000 31 #define R92C_RXDW0_INFOSZ_S 16 32 #define R92C_RXDW0_CIPHER_M 0x00700000 33 #define R92C_RXDW0_CIPHER_S 20 34 #define R92C_RXDW0_QOS 0x00800000 35 #define R92C_RXDW0_SHIFT_M 0x03000000 36 #define R92C_RXDW0_SHIFT_S 24 37 #define R92C_RXDW0_PHYST 0x04000000 38 #define R92C_RXDW0_SWDEC 0x08000000 39 #define R92C_RXDW0_LS 0x10000000 40 #define R92C_RXDW0_FS 0x20000000 41 #define R92C_RXDW0_EOR 0x40000000 42 #define R92C_RXDW0_OWN 0x80000000 43 44 uint32_t rxdw1; 45 #define R92C_RXDW1_MACID_M 0x0000001f 46 #define R92C_RXDW1_MACID_S 0 47 #define R92C_RXDW1_AMSDU 0x00002000 48 #define R92C_RXDW1_AMPDU_MORE 0x00004000 49 #define R92C_RXDW1_AMPDU 0x00008000 50 #define R92C_RXDW1_MC 0x40000000 51 #define R92C_RXDW1_BC 0x80000000 52 53 uint32_t rxdw2; 54 uint32_t rxdw3; 55 #define R92C_RXDW3_RATE_M 0x0000003f 56 #define R92C_RXDW3_RATE_S 0 57 #define R92C_RXDW3_HT 0x00000040 58 #define R92C_RXDW3_SPLCP 0x00000100 59 #define R92C_RXDW3_HT40 0x00000200 60 #define R92C_RXDW3_HTC 0x00000400 61 #define R92C_RXDW3_BSSID_FIT_M 0x00003000 62 #define R92C_RXDW3_BSSID_FIT_S 12 63 64 uint32_t rxdw4; 65 uint32_t tsf_low; 66 } __packed __attribute__((aligned(4))); 67 68 /* Rx PHY CCK descriptor. */ 69 struct r92c_rx_cck { 70 uint8_t adc_pwdb[4]; 71 uint8_t sq_rpt; 72 uint8_t agc_rpt; 73 } __packed; 74 75 /* Rx PHY descriptor. */ 76 struct r92c_rx_phystat { 77 uint8_t trsw_gain[4]; 78 uint8_t pwdb_all; 79 uint8_t cfosho[4]; 80 uint8_t cfotail[4]; 81 uint8_t rxevm[2]; 82 uint8_t rxsnr[4]; 83 uint8_t pdsnr[2]; 84 uint8_t csi_current[2]; 85 uint8_t csi_target[2]; 86 uint8_t sigevm; 87 uint8_t max_ex_pwr; 88 uint8_t phy_byte28; 89 #define R92C_PHY_BYTE28_ANTSEL 0x01 90 #define R92C_PHY_BYTE28_ANTSEL_B 0x02 91 #define R92C_PHY_BYTE28_ANT_TRAIN_EN 0x04 92 #define R92C_PHY_BYTE28_IDLE_LONG 0x08 93 #define R92C_PHY_BYTE28_RXSC_M 0x30 94 #define R92C_PHY_BYTE28_RXSC_S 4 95 #define R92C_PHY_BYTE28_SGI_EN 0x40 96 #define R92C_PHY_BYTE28_EX_INTF_FLG 0x80 97 } __packed; 98 99 #endif /* R92C_RX_DESC_H */ 100