xref: /freebsd/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2057.h (revision 2ff63af9b88c7413b7d71715b5532625752a248e)
1 /*
2 
3   Broadcom B43 wireless driver
4   IEEE 802.11n PHY data tables
5 
6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
7   Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
8 
9   This program is free software; you can redistribute it and/or modify
10   it under the terms of the GNU General Public License as published by
11   the Free Software Foundation; either version 2 of the License, or
12   (at your option) any later version.
13 
14   This program is distributed in the hope that it will be useful,
15   but WITHOUT ANY WARRANTY; without even the implied warranty of
16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17   GNU General Public License for more details.
18 
19   You should have received a copy of the GNU General Public License
20   along with this program; see the file COPYING.  If not, write to
21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22   Boston, MA 02110-1301, USA.
23 
24 */
25 
26 /*
27  */
28 
29 #ifndef	__IF_BWN_RADIO_2057_H__
30 #define	__IF_BWN_RADIO_2057_H__
31 
32 #define R2057_DACBUF_VINCM_CORE0		0x000
33 #define R2057_IDCODE				0x001
34 #define R2057_RCCAL_MASTER			0x002
35 #define R2057_RCCAL_CAP_SIZE			0x003
36 #define R2057_RCAL_CONFIG			0x004
37 #define R2057_GPAIO_CONFIG			0x005
38 #define R2057_GPAIO_SEL1			0x006
39 #define R2057_GPAIO_SEL0			0x007
40 #define R2057_CLPO_CONFIG			0x008
41 #define R2057_BANDGAP_CONFIG			0x009
42 #define R2057_BANDGAP_RCAL_TRIM			0x00a
43 #define R2057_AFEREG_CONFIG			0x00b
44 #define R2057_TEMPSENSE_CONFIG			0x00c
45 #define R2057_XTAL_CONFIG1			0x00d
46 #define R2057_XTAL_ICORE_SIZE			0x00e
47 #define R2057_XTAL_BUF_SIZE			0x00f
48 #define R2057_XTAL_PULLCAP_SIZE			0x010
49 #define R2057_RFPLL_MASTER			0x011
50 #define R2057_VCOMONITOR_VTH_L			0x012
51 #define R2057_VCOMONITOR_VTH_H			0x013
52 #define R2057_VCOCAL_BIASRESET_RFPLLREG_VOUT	0x014
53 #define R2057_VCO_VARCSIZE_IDAC			0x015
54 #define R2057_VCOCAL_COUNTVAL0			0x016
55 #define R2057_VCOCAL_COUNTVAL1			0x017
56 #define R2057_VCOCAL_INTCLK_COUNT		0x018
57 #define R2057_VCOCAL_MASTER			0x019
58 #define R2057_VCOCAL_NUMCAPCHANGE		0x01a
59 #define R2057_VCOCAL_WINSIZE			0x01b
60 #define R2057_VCOCAL_DELAY_AFTER_REFRESH	0x01c
61 #define R2057_VCOCAL_DELAY_AFTER_CLOSELOOP	0x01d
62 #define R2057_VCOCAL_DELAY_AFTER_OPENLOOP	0x01e
63 #define R2057_VCOCAL_DELAY_BEFORE_OPENLOOP	0x01f
64 #define R2057_VCO_FORCECAPEN_FORCECAP1		0x020
65 #define R2057_VCO_FORCECAP0			0x021
66 #define R2057_RFPLL_REFMASTER_SPAREXTALSIZE	0x022
67 #define R2057_RFPLL_PFD_RESET_PW		0x023
68 #define R2057_RFPLL_LOOPFILTER_R2		0x024
69 #define R2057_RFPLL_LOOPFILTER_R1		0x025
70 #define R2057_RFPLL_LOOPFILTER_C3		0x026
71 #define R2057_RFPLL_LOOPFILTER_C2		0x027
72 #define R2057_RFPLL_LOOPFILTER_C1		0x028
73 #define R2057_CP_KPD_IDAC			0x029
74 #define R2057_RFPLL_IDACS			0x02a
75 #define R2057_RFPLL_MISC_EN			0x02b
76 #define R2057_RFPLL_MMD0			0x02c
77 #define R2057_RFPLL_MMD1			0x02d
78 #define R2057_RFPLL_MISC_CAL_RESETN		0x02e
79 #define R2057_JTAGXTAL_SIZE_CPBIAS_FILTRES	0x02f
80 #define R2057_VCO_ALCREF_BBPLLXTAL_SIZE		0x030
81 #define R2057_VCOCAL_READCAP0			0x031
82 #define R2057_VCOCAL_READCAP1			0x032
83 #define R2057_VCOCAL_STATUS			0x033
84 #define R2057_LOGEN_PUS				0x034
85 #define R2057_LOGEN_PTAT_RESETS			0x035
86 #define R2057_VCOBUF_IDACS			0x036
87 #define R2057_VCOBUF_TUNE			0x037
88 #define R2057_CMOSBUF_TX2GQ_IDACS		0x038
89 #define R2057_CMOSBUF_TX2GI_IDACS		0x039
90 #define R2057_CMOSBUF_TX5GQ_IDACS		0x03a
91 #define R2057_CMOSBUF_TX5GI_IDACS		0x03b
92 #define R2057_CMOSBUF_RX2GQ_IDACS		0x03c
93 #define R2057_CMOSBUF_RX2GI_IDACS		0x03d
94 #define R2057_CMOSBUF_RX5GQ_IDACS		0x03e
95 #define R2057_CMOSBUF_RX5GI_IDACS		0x03f
96 #define R2057_LOGEN_MX2G_IDACS			0x040
97 #define R2057_LOGEN_MX2G_TUNE			0x041
98 #define R2057_LOGEN_MX5G_IDACS			0x042
99 #define R2057_LOGEN_MX5G_TUNE			0x043
100 #define R2057_LOGEN_MX5G_RCCR			0x044
101 #define R2057_LOGEN_INDBUF2G_IDAC		0x045
102 #define R2057_LOGEN_INDBUF2G_IBOOST		0x046
103 #define R2057_LOGEN_INDBUF2G_TUNE		0x047
104 #define R2057_LOGEN_INDBUF5G_IDAC		0x048
105 #define R2057_LOGEN_INDBUF5G_IBOOST		0x049
106 #define R2057_LOGEN_INDBUF5G_TUNE		0x04a
107 #define R2057_CMOSBUF_TX_RCCR			0x04b
108 #define R2057_CMOSBUF_RX_RCCR			0x04c
109 #define R2057_LOGEN_SEL_PKDET			0x04d
110 #define R2057_CMOSBUF_SHAREIQ_PTAT		0x04e
111 
112 /* MISC core 0 */
113 #define R2057_RXTXBIAS_CONFIG_CORE0		0x04f
114 #define R2057_TXGM_TXRF_PUS_CORE0		0x050
115 #define R2057_TXGM_IDAC_BLEED_CORE0		0x051
116 #define R2057_TXGM_GAIN_CORE0			0x056
117 #define R2057_TXGM2G_PKDET_PUS_CORE0		0x057
118 #define R2057_PAD2G_PTATS_CORE0			0x058
119 #define R2057_PAD2G_IDACS_CORE0			0x059
120 #define R2057_PAD2G_BOOST_PU_CORE0		0x05a
121 #define R2057_PAD2G_CASCV_GAIN_CORE0		0x05b
122 #define R2057_TXMIX2G_TUNE_BOOST_PU_CORE0	0x05c
123 #define R2057_TXMIX2G_LODC_CORE0		0x05d
124 #define R2057_PAD2G_TUNE_PUS_CORE0		0x05e
125 #define R2057_IPA2G_GAIN_CORE0			0x05f
126 #define R2057_TSSI2G_SPARE1_CORE0		0x060
127 #define R2057_TSSI2G_SPARE2_CORE0		0x061
128 #define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE0	0x062
129 #define R2057_IPA2G_IMAIN_CORE0			0x063
130 #define R2057_IPA2G_CASCONV_CORE0		0x064
131 #define R2057_IPA2G_CASCOFFV_CORE0		0x065
132 #define R2057_IPA2G_BIAS_FILTER_CORE0		0x066
133 #define R2057_TX5G_PKDET_CORE0			0x069
134 #define R2057_PGA_PTAT_TXGM5G_PU_CORE0		0x06a
135 #define R2057_PAD5G_PTATS1_CORE0		0x06b
136 #define R2057_PAD5G_CLASS_PTATS2_CORE0		0x06c
137 #define R2057_PGA_BOOSTPTAT_IMAIN_CORE0		0x06d
138 #define R2057_PAD5G_CASCV_IMAIN_CORE0		0x06e
139 #define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0	0x06f
140 #define R2057_PGA_BOOST_TUNE_CORE0		0x070
141 #define R2057_PGA_GAIN_CORE0			0x071
142 #define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0	0x072
143 #define R2057_TXMIX5G_BOOST_TUNE_CORE0		0x073
144 #define R2057_PAD5G_TUNE_MISC_PUS_CORE0		0x074
145 #define R2057_IPA5G_IAUX_CORE0			0x075
146 #define R2057_IPA5G_GAIN_CORE0			0x076
147 #define R2057_TSSI5G_SPARE1_CORE0		0x077
148 #define R2057_TSSI5G_SPARE2_CORE0		0x078
149 #define R2057_IPA5G_CASCOFFV_PU_CORE0		0x079
150 #define R2057_IPA5G_PTAT_CORE0			0x07a
151 #define R2057_IPA5G_IMAIN_CORE0			0x07b
152 #define R2057_IPA5G_CASCONV_CORE0		0x07c
153 #define R2057_IPA5G_BIAS_FILTER_CORE0		0x07d
154 #define R2057_PAD_BIAS_FILTER_BWS_CORE0		0x080
155 #define R2057_TR2G_CONFIG1_CORE0_NU		0x081
156 #define R2057_TR2G_CONFIG2_CORE0_NU		0x082
157 #define R2057_LNA5G_RFEN_CORE0			0x083
158 #define R2057_TR5G_CONFIG2_CORE0_NU		0x084
159 #define R2057_RXRFBIAS_IBOOST_PU_CORE0		0x085
160 #define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0	0x086
161 #define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE0	0x087
162 #define R2057_RXMIX_ICORE_RXGM_IAUX_CORE0	0x088
163 #define R2057_RXMIX_CMFBITAIL_PU_CORE0		0x089
164 #define R2057_LNA2_IMAIN_PTAT_PU_CORE0		0x08a
165 #define R2057_LNA2_IAUX_PTAT_CORE0		0x08b
166 #define R2057_LNA1_IMAIN_PTAT_PU_CORE0		0x08c
167 #define R2057_LNA15G_INPUT_MATCH_TUNE_CORE0	0x08d
168 #define R2057_RXRFBIAS_BANDSEL_CORE0		0x08e
169 #define R2057_TIA_CONFIG_CORE0			0x08f
170 #define R2057_TIA_IQGAIN_CORE0			0x090
171 #define R2057_TIA_IBIAS2_CORE0			0x091
172 #define R2057_TIA_IBIAS1_CORE0			0x092
173 #define R2057_TIA_SPARE_Q_CORE0			0x093
174 #define R2057_TIA_SPARE_I_CORE0			0x094
175 #define R2057_RXMIX2G_PUS_CORE0			0x095
176 #define R2057_RXMIX2G_VCMREFS_CORE0		0x096
177 #define R2057_RXMIX2G_LODC_QI_CORE0		0x097
178 #define R2057_W12G_BW_LNA2G_PUS_CORE0		0x098
179 #define R2057_LNA2G_GAIN_CORE0			0x099
180 #define R2057_LNA2G_TUNE_CORE0			0x09a
181 #define R2057_RXMIX5G_PUS_CORE0			0x09b
182 #define R2057_RXMIX5G_VCMREFS_CORE0		0x09c
183 #define R2057_RXMIX5G_LODC_QI_CORE0		0x09d
184 #define R2057_W15G_BW_LNA5G_PUS_CORE0		0x09e
185 #define R2057_LNA5G_GAIN_CORE0			0x09f
186 #define R2057_LNA5G_TUNE_CORE0			0x0a0
187 #define R2057_LPFSEL_TXRX_RXBB_PUS_CORE0	0x0a1
188 #define R2057_RXBB_BIAS_MASTER_CORE0		0x0a2
189 #define R2057_RXBB_VGABUF_IDACS_CORE0		0x0a3
190 #define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE0	0x0a4
191 #define R2057_TXBUF_VINCM_CORE0			0x0a5
192 #define R2057_TXBUF_IDACS_CORE0			0x0a6
193 #define R2057_LPF_RESP_RXBUF_BW_CORE0		0x0a7
194 #define R2057_RXBB_CC_CORE0			0x0a8
195 #define R2057_RXBB_SPARE3_CORE0			0x0a9
196 #define R2057_RXBB_RCCAL_HPC_CORE0		0x0aa
197 #define R2057_LPF_IDACS_CORE0			0x0ab
198 #define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0	0x0ac
199 #define R2057_TXBUF_GAIN_CORE0			0x0ad
200 #define R2057_AFELOOPBACK_AACI_RESP_CORE0	0x0ae
201 #define R2057_RXBUF_DEGEN_CORE0			0x0af
202 #define R2057_RXBB_SPARE2_CORE0			0x0b0
203 #define R2057_RXBB_SPARE1_CORE0			0x0b1
204 #define R2057_RSSI_MASTER_CORE0			0x0b2
205 #define R2057_W2_MASTER_CORE0			0x0b3
206 #define R2057_NB_MASTER_CORE0			0x0b4
207 #define R2057_W2_IDACS0_Q_CORE0			0x0b5
208 #define R2057_W2_IDACS1_Q_CORE0			0x0b6
209 #define R2057_W2_IDACS0_I_CORE0			0x0b7
210 #define R2057_W2_IDACS1_I_CORE0			0x0b8
211 #define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE0	0x0b9
212 #define R2057_NB_IDACS_Q_CORE0			0x0ba
213 #define R2057_NB_IDACS_I_CORE0			0x0bb
214 #define R2057_BACKUP4_CORE0			0x0c1
215 #define R2057_BACKUP3_CORE0			0x0c2
216 #define R2057_BACKUP2_CORE0			0x0c3
217 #define R2057_BACKUP1_CORE0			0x0c4
218 #define R2057_SPARE16_CORE0			0x0c5
219 #define R2057_SPARE15_CORE0			0x0c6
220 #define R2057_SPARE14_CORE0			0x0c7
221 #define R2057_SPARE13_CORE0			0x0c8
222 #define R2057_SPARE12_CORE0			0x0c9
223 #define R2057_SPARE11_CORE0			0x0ca
224 #define R2057_TX2G_BIAS_RESETS_CORE0		0x0cb
225 #define R2057_TX5G_BIAS_RESETS_CORE0		0x0cc
226 #define R2057_IQTEST_SEL_PU			0x0cd
227 #define R2057_XTAL_CONFIG2			0x0ce
228 #define R2057_BUFS_MISC_LPFBW_CORE0		0x0cf
229 #define R2057_TXLPF_RCCAL_CORE0			0x0d0
230 #define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0	0x0d1
231 #define R2057_LPF_GAIN_CORE0			0x0d2
232 #define R2057_DACBUF_IDACS_BW_CORE0		0x0d3
233 
234 /* MISC core 1 */
235 #define R2057_RXTXBIAS_CONFIG_CORE1		0x0d4
236 #define R2057_TXGM_TXRF_PUS_CORE1		0x0d5
237 #define R2057_TXGM_IDAC_BLEED_CORE1		0x0d6
238 #define R2057_TXGM_GAIN_CORE1			0x0db
239 #define R2057_TXGM2G_PKDET_PUS_CORE1		0x0dc
240 #define R2057_PAD2G_PTATS_CORE1			0x0dd
241 #define R2057_PAD2G_IDACS_CORE1			0x0de
242 #define R2057_PAD2G_BOOST_PU_CORE1		0x0df
243 #define R2057_PAD2G_CASCV_GAIN_CORE1		0x0e0
244 #define R2057_TXMIX2G_TUNE_BOOST_PU_CORE1	0x0e1
245 #define R2057_TXMIX2G_LODC_CORE1		0x0e2
246 #define R2057_PAD2G_TUNE_PUS_CORE1		0x0e3
247 #define R2057_IPA2G_GAIN_CORE1			0x0e4
248 #define R2057_TSSI2G_SPARE1_CORE1		0x0e5
249 #define R2057_TSSI2G_SPARE2_CORE1		0x0e6
250 #define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE1	0x0e7
251 #define R2057_IPA2G_IMAIN_CORE1			0x0e8
252 #define R2057_IPA2G_CASCONV_CORE1		0x0e9
253 #define R2057_IPA2G_CASCOFFV_CORE1		0x0ea
254 #define R2057_IPA2G_BIAS_FILTER_CORE1		0x0eb
255 #define R2057_TX5G_PKDET_CORE1			0x0ee
256 #define R2057_PGA_PTAT_TXGM5G_PU_CORE1		0x0ef
257 #define R2057_PAD5G_PTATS1_CORE1		0x0f0
258 #define R2057_PAD5G_CLASS_PTATS2_CORE1		0x0f1
259 #define R2057_PGA_BOOSTPTAT_IMAIN_CORE1		0x0f2
260 #define R2057_PAD5G_CASCV_IMAIN_CORE1		0x0f3
261 #define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1	0x0f4
262 #define R2057_PGA_BOOST_TUNE_CORE1		0x0f5
263 #define R2057_PGA_GAIN_CORE1			0x0f6
264 #define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1	0x0f7
265 #define R2057_TXMIX5G_BOOST_TUNE_CORE1		0x0f8
266 #define R2057_PAD5G_TUNE_MISC_PUS_CORE1		0x0f9
267 #define R2057_IPA5G_IAUX_CORE1			0x0fa
268 #define R2057_IPA5G_GAIN_CORE1			0x0fb
269 #define R2057_TSSI5G_SPARE1_CORE1		0x0fc
270 #define R2057_TSSI5G_SPARE2_CORE1		0x0fd
271 #define R2057_IPA5G_CASCOFFV_PU_CORE1		0x0fe
272 #define R2057_IPA5G_PTAT_CORE1			0x0ff
273 #define R2057_IPA5G_IMAIN_CORE1			0x100
274 #define R2057_IPA5G_CASCONV_CORE1		0x101
275 #define R2057_IPA5G_BIAS_FILTER_CORE1		0x102
276 #define R2057_PAD_BIAS_FILTER_BWS_CORE1		0x105
277 #define R2057_TR2G_CONFIG1_CORE1_NU		0x106
278 #define R2057_TR2G_CONFIG2_CORE1_NU		0x107
279 #define R2057_LNA5G_RFEN_CORE1			0x108
280 #define R2057_TR5G_CONFIG2_CORE1_NU		0x109
281 #define R2057_RXRFBIAS_IBOOST_PU_CORE1		0x10a
282 #define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1	0x10b
283 #define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE1	0x10c
284 #define R2057_RXMIX_ICORE_RXGM_IAUX_CORE1	0x10d
285 #define R2057_RXMIX_CMFBITAIL_PU_CORE1		0x10e
286 #define R2057_LNA2_IMAIN_PTAT_PU_CORE1		0x10f
287 #define R2057_LNA2_IAUX_PTAT_CORE1		0x110
288 #define R2057_LNA1_IMAIN_PTAT_PU_CORE1		0x111
289 #define R2057_LNA15G_INPUT_MATCH_TUNE_CORE1	0x112
290 #define R2057_RXRFBIAS_BANDSEL_CORE1		0x113
291 #define R2057_TIA_CONFIG_CORE1			0x114
292 #define R2057_TIA_IQGAIN_CORE1			0x115
293 #define R2057_TIA_IBIAS2_CORE1			0x116
294 #define R2057_TIA_IBIAS1_CORE1			0x117
295 #define R2057_TIA_SPARE_Q_CORE1			0x118
296 #define R2057_TIA_SPARE_I_CORE1			0x119
297 #define R2057_RXMIX2G_PUS_CORE1			0x11a
298 #define R2057_RXMIX2G_VCMREFS_CORE1		0x11b
299 #define R2057_RXMIX2G_LODC_QI_CORE1		0x11c
300 #define R2057_W12G_BW_LNA2G_PUS_CORE1		0x11d
301 #define R2057_LNA2G_GAIN_CORE1			0x11e
302 #define R2057_LNA2G_TUNE_CORE1			0x11f
303 #define R2057_RXMIX5G_PUS_CORE1			0x120
304 #define R2057_RXMIX5G_VCMREFS_CORE1		0x121
305 #define R2057_RXMIX5G_LODC_QI_CORE1		0x122
306 #define R2057_W15G_BW_LNA5G_PUS_CORE1		0x123
307 #define R2057_LNA5G_GAIN_CORE1			0x124
308 #define R2057_LNA5G_TUNE_CORE1			0x125
309 #define R2057_LPFSEL_TXRX_RXBB_PUS_CORE1	0x126
310 #define R2057_RXBB_BIAS_MASTER_CORE1		0x127
311 #define R2057_RXBB_VGABUF_IDACS_CORE1		0x128
312 #define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE1	0x129
313 #define R2057_TXBUF_VINCM_CORE1			0x12a
314 #define R2057_TXBUF_IDACS_CORE1			0x12b
315 #define R2057_LPF_RESP_RXBUF_BW_CORE1		0x12c
316 #define R2057_RXBB_CC_CORE1			0x12d
317 #define R2057_RXBB_SPARE3_CORE1			0x12e
318 #define R2057_RXBB_RCCAL_HPC_CORE1		0x12f
319 #define R2057_LPF_IDACS_CORE1			0x130
320 #define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1	0x131
321 #define R2057_TXBUF_GAIN_CORE1			0x132
322 #define R2057_AFELOOPBACK_AACI_RESP_CORE1	0x133
323 #define R2057_RXBUF_DEGEN_CORE1			0x134
324 #define R2057_RXBB_SPARE2_CORE1			0x135
325 #define R2057_RXBB_SPARE1_CORE1			0x136
326 #define R2057_RSSI_MASTER_CORE1			0x137
327 #define R2057_W2_MASTER_CORE1			0x138
328 #define R2057_NB_MASTER_CORE1			0x139
329 #define R2057_W2_IDACS0_Q_CORE1			0x13a
330 #define R2057_W2_IDACS1_Q_CORE1			0x13b
331 #define R2057_W2_IDACS0_I_CORE1			0x13c
332 #define R2057_W2_IDACS1_I_CORE1			0x13d
333 #define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE1	0x13e
334 #define R2057_NB_IDACS_Q_CORE1			0x13f
335 #define R2057_NB_IDACS_I_CORE1			0x140
336 #define R2057_BACKUP4_CORE1			0x146
337 #define R2057_BACKUP3_CORE1			0x147
338 #define R2057_BACKUP2_CORE1			0x148
339 #define R2057_BACKUP1_CORE1			0x149
340 #define R2057_SPARE16_CORE1			0x14a
341 #define R2057_SPARE15_CORE1			0x14b
342 #define R2057_SPARE14_CORE1			0x14c
343 #define R2057_SPARE13_CORE1			0x14d
344 #define R2057_SPARE12_CORE1			0x14e
345 #define R2057_SPARE11_CORE1			0x14f
346 #define R2057_TX2G_BIAS_RESETS_CORE1		0x150
347 #define R2057_TX5G_BIAS_RESETS_CORE1		0x151
348 #define R2057_SPARE8_CORE1			0x152
349 #define R2057_SPARE7_CORE1			0x153
350 #define R2057_BUFS_MISC_LPFBW_CORE1		0x154
351 #define R2057_TXLPF_RCCAL_CORE1			0x155
352 #define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1	0x156
353 #define R2057_LPF_GAIN_CORE1			0x157
354 #define R2057_DACBUF_IDACS_BW_CORE1		0x158
355 
356 #define R2057_DACBUF_VINCM_CORE1		0x159
357 #define R2057_RCCAL_START_R1_Q1_P1		0x15a
358 #define R2057_RCCAL_X1				0x15b
359 #define R2057_RCCAL_TRC0			0x15c
360 #define R2057_RCCAL_TRC1			0x15d
361 #define R2057_RCCAL_DONE_OSCCAP			0x15e
362 #define R2057_RCCAL_N0_0			0x15f
363 #define R2057_RCCAL_N0_1			0x160
364 #define R2057_RCCAL_N1_0			0x161
365 #define R2057_RCCAL_N1_1			0x162
366 #define R2057_RCAL_STATUS			0x163
367 #define R2057_XTALPUOVR_PINCTRL			0x164
368 #define R2057_OVR_REG0				0x165
369 #define R2057_OVR_REG1				0x166
370 #define R2057_OVR_REG2				0x167
371 #define R2057_OVR_REG3				0x168
372 #define R2057_OVR_REG4				0x169
373 #define R2057_RCCAL_SCAP_VAL			0x16a
374 #define R2057_RCCAL_BCAP_VAL			0x16b
375 #define R2057_RCCAL_HPC_VAL			0x16c
376 #define R2057_RCCAL_OVERRIDES			0x16d
377 
378 /* TX core 0 */
379 #define R2057_TX0_IQCAL_GAIN_BW			0x170
380 #define R2057_TX0_LOFT_FINE_I			0x171
381 #define R2057_TX0_LOFT_FINE_Q			0x172
382 #define R2057_TX0_LOFT_COARSE_I			0x173
383 #define R2057_TX0_LOFT_COARSE_Q			0x174
384 #define R2057_TX0_TX_SSI_MASTER			0x175
385 #define R2057_TX0_IQCAL_VCM_HG			0x176
386 #define R2057_TX0_IQCAL_IDAC			0x177
387 #define R2057_TX0_TSSI_VCM			0x178
388 #define R2057_TX0_TX_SSI_MUX			0x179
389 #define R2057_TX0_TSSIA				0x17a
390 #define R2057_TX0_TSSIG				0x17b
391 #define R2057_TX0_TSSI_MISC1			0x17c
392 #define R2057_TX0_TXRXCOUPLE_2G_ATTEN		0x17d
393 #define R2057_TX0_TXRXCOUPLE_2G_PWRUP		0x17e
394 #define R2057_TX0_TXRXCOUPLE_5G_ATTEN		0x17f
395 #define R2057_TX0_TXRXCOUPLE_5G_PWRUP		0x180
396 
397 /* TX core 1 */
398 #define R2057_TX1_IQCAL_GAIN_BW			0x190
399 #define R2057_TX1_LOFT_FINE_I			0x191
400 #define R2057_TX1_LOFT_FINE_Q			0x192
401 #define R2057_TX1_LOFT_COARSE_I			0x193
402 #define R2057_TX1_LOFT_COARSE_Q			0x194
403 #define R2057_TX1_TX_SSI_MASTER			0x195
404 #define R2057_TX1_IQCAL_VCM_HG			0x196
405 #define R2057_TX1_IQCAL_IDAC			0x197
406 #define R2057_TX1_TSSI_VCM			0x198
407 #define R2057_TX1_TX_SSI_MUX			0x199
408 #define R2057_TX1_TSSIA				0x19a
409 #define R2057_TX1_TSSIG				0x19b
410 #define R2057_TX1_TSSI_MISC1			0x19c
411 #define R2057_TX1_TXRXCOUPLE_2G_ATTEN		0x19d
412 #define R2057_TX1_TXRXCOUPLE_2G_PWRUP		0x19e
413 #define R2057_TX1_TXRXCOUPLE_5G_ATTEN		0x19f
414 #define R2057_TX1_TXRXCOUPLE_5G_PWRUP		0x1a0
415 
416 #define R2057_AFE_VCM_CAL_MASTER_CORE0		0x1a1
417 #define R2057_AFE_SET_VCM_I_CORE0		0x1a2
418 #define R2057_AFE_SET_VCM_Q_CORE0		0x1a3
419 #define R2057_AFE_STATUS_VCM_IQADC_CORE0	0x1a4
420 #define R2057_AFE_STATUS_VCM_I_CORE0		0x1a5
421 #define R2057_AFE_STATUS_VCM_Q_CORE0		0x1a6
422 #define R2057_AFE_VCM_CAL_MASTER_CORE1		0x1a7
423 #define R2057_AFE_SET_VCM_I_CORE1		0x1a8
424 #define R2057_AFE_SET_VCM_Q_CORE1		0x1a9
425 #define R2057_AFE_STATUS_VCM_IQADC_CORE1	0x1aa
426 #define R2057_AFE_STATUS_VCM_I_CORE1		0x1ab
427 #define R2057_AFE_STATUS_VCM_Q_CORE1		0x1ac
428 
429 #define R2057v7_DACBUF_VINCM_CORE0		0x1ad
430 #define R2057v7_RCCAL_MASTER			0x1ae
431 #define R2057v7_TR2G_CONFIG3_CORE0_NU		0x1af
432 #define R2057v7_TR2G_CONFIG3_CORE1_NU		0x1b0
433 #define R2057v7_LOGEN_PUS1			0x1b1
434 #define R2057v7_OVR_REG5			0x1b2
435 #define R2057v7_OVR_REG6			0x1b3
436 #define R2057v7_OVR_REG7			0x1b4
437 #define R2057v7_OVR_REG8			0x1b5
438 #define R2057v7_OVR_REG9			0x1b6
439 #define R2057v7_OVR_REG10			0x1b7
440 #define R2057v7_OVR_REG11			0x1b8
441 #define R2057v7_OVR_REG12			0x1b9
442 #define R2057v7_OVR_REG13			0x1ba
443 #define R2057v7_OVR_REG14			0x1bb
444 #define R2057v7_OVR_REG15			0x1bc
445 #define R2057v7_OVR_REG16			0x1bd
446 #define R2057v7_OVR_REG1			0x1be
447 #define R2057v7_OVR_REG18			0x1bf
448 #define R2057v7_OVR_REG19			0x1c0
449 #define R2057v7_OVR_REG20			0x1c1
450 #define R2057v7_OVR_REG21			0x1c2
451 #define R2057v7_OVR_REG2			0x1c3
452 #define R2057v7_OVR_REG23			0x1c4
453 #define R2057v7_OVR_REG24			0x1c5
454 #define R2057v7_OVR_REG25			0x1c6
455 #define R2057v7_OVR_REG26			0x1c7
456 #define R2057v7_OVR_REG27			0x1c8
457 #define R2057v7_OVR_REG28			0x1c9
458 #define R2057v7_IQTEST_SEL_PU2			0x1ca
459 
460 #define R2057_VCM_MASK				0x7
461 
462 struct bwn_nphy_chantabent_rev7 {
463 	/* The channel frequency in MHz */
464 	uint16_t freq;
465 	/* Radio regs values on channelswitch */
466 	uint8_t radio_vcocal_countval0;
467 	uint8_t radio_vcocal_countval1;
468 	uint8_t radio_rfpll_refmaster_sparextalsize;
469 	uint8_t radio_rfpll_loopfilter_r1;
470 	uint8_t radio_rfpll_loopfilter_c2;
471 	uint8_t radio_rfpll_loopfilter_c1;
472 	uint8_t radio_cp_kpd_idac;
473 	uint8_t radio_rfpll_mmd0;
474 	uint8_t radio_rfpll_mmd1;
475 	uint8_t radio_vcobuf_tune;
476 	uint8_t radio_logen_mx2g_tune;
477 	uint8_t radio_logen_mx5g_tune;
478 	uint8_t radio_logen_indbuf2g_tune;
479 	uint8_t radio_logen_indbuf5g_tune;
480 	uint8_t radio_txmix2g_tune_boost_pu_core0;
481 	uint8_t radio_pad2g_tune_pus_core0;
482 	uint8_t radio_pga_boost_tune_core0;
483 	uint8_t radio_txmix5g_boost_tune_core0;
484 	uint8_t radio_pad5g_tune_misc_pus_core0;
485 	uint8_t radio_lna2g_tune_core0;
486 	uint8_t radio_lna5g_tune_core0;
487 	uint8_t radio_txmix2g_tune_boost_pu_core1;
488 	uint8_t radio_pad2g_tune_pus_core1;
489 	uint8_t radio_pga_boost_tune_core1;
490 	uint8_t radio_txmix5g_boost_tune_core1;
491 	uint8_t radio_pad5g_tune_misc_pus_core1;
492 	uint8_t radio_lna2g_tune_core1;
493 	uint8_t radio_lna5g_tune_core1;
494 	/* PHY res values on channelswitch */
495 	struct bwn_phy_n_sfo_cfg phy_regs;
496 };
497 
498 struct bwn_nphy_chantabent_rev7_2g {
499 	/* The channel frequency in MHz */
500 	uint16_t freq;
501 	/* Radio regs values on channelswitch */
502 	uint8_t radio_vcocal_countval0;
503 	uint8_t radio_vcocal_countval1;
504 	uint8_t radio_rfpll_refmaster_sparextalsize;
505 	uint8_t radio_rfpll_loopfilter_r1;
506 	uint8_t radio_rfpll_loopfilter_c2;
507 	uint8_t radio_rfpll_loopfilter_c1;
508 	uint8_t radio_cp_kpd_idac;
509 	uint8_t radio_rfpll_mmd0;
510 	uint8_t radio_rfpll_mmd1;
511 	uint8_t radio_vcobuf_tune;
512 	uint8_t radio_logen_mx2g_tune;
513 	uint8_t radio_logen_indbuf2g_tune;
514 	uint8_t radio_txmix2g_tune_boost_pu_core0;
515 	uint8_t radio_pad2g_tune_pus_core0;
516 	uint8_t radio_lna2g_tune_core0;
517 	uint8_t radio_txmix2g_tune_boost_pu_core1;
518 	uint8_t radio_pad2g_tune_pus_core1;
519 	uint8_t radio_lna2g_tune_core1;
520 	/* PHY regs values on channelswitch */
521 	struct bwn_phy_n_sfo_cfg phy_regs;
522 };
523 
524 void r2057_upload_inittabs(struct bwn_mac *mac);
525 
526 void r2057_get_chantabent_rev7(struct bwn_mac *mac, uint16_t freq,
527 			       const struct bwn_nphy_chantabent_rev7 **tabent_r7,
528 			       const struct bwn_nphy_chantabent_rev7_2g **tabent_r7_2g);
529 
530 #endif	/* IF_BWN_RADIO_2057_H_ */
531