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Searched refs:PtrReg (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp333 Register PtrReg = Store.getPointerReg(); in applySplitStoreZero128() local
335 auto HighPtr = B.buildPtrAdd(MRI.getType(PtrReg), PtrReg, in applySplitStoreZero128()
340 B.buildStore(Zero, PtrReg, *LowMMO); in applySplitStoreZero128()
843 Register PtrReg = St->getPointerReg(); in optimizeConsecutiveMemOpAddressing() local
845 PtrReg, MRI, in optimizeConsecutiveMemOpAddressing()
847 GPtrAdd *PtrAdd = cast<GPtrAdd>(MRI.getVRegDef(PtrReg)); in optimizeConsecutiveMemOpAddressing()
H A DAArch64InstructionSelector.cpp3058 const Register PtrReg = LdSt.getPointerReg(); in select() local
3059 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); in select()
3063 assert(MRI.getType(PtrReg).isPointer() && in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp422 Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy); in lowerParameter() local
423 lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]); in lowerParameter()
442 B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO); in lowerParameter()
563 Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy); in lowerFormalArgumentsKernel() local
564 lowerParameterPtr(PtrReg, B, ArgOffset); in lowerFormalArgumentsKernel()
566 B.buildAddrSpaceCast(VRegs[i][0], PtrReg); in lowerFormalArgumentsKernel()
H A DAMDGPURegisterBankInfo.cpp1089 Register PtrReg = MI.getOperand(1).getReg(); in applyMappingLoad() local
1099 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1103 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1107 B.buildLoadFromOffset(MI.getOperand(0), PtrReg, *MMO, 0); in applyMappingLoad()
1121 auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0); in applyMappingLoad()
3342 Register PtrReg = MI.getOperand(1).getReg(); in applyMappingImpl() local
3343 unsigned AS = MRI.getType(PtrReg).getAddressSpace(); in applyMappingImpl()
3507 Register PtrReg = MI.getOperand(0).getReg(); in applyMappingImpl() local
3508 unsigned PtrBank = getRegBankID(PtrReg, MRI, AMDGPU::SGPRRegBankID); in applyMappingImpl()
3513 unsigned AS = MRI.getType(PtrReg).getAddressSpace(); in applyMappingImpl()
[all …]
H A DAMDGPULegalizerInfo.cpp3128 Register PtrReg = MI.getOperand(1).getReg(); in legalizeLoad() local
3129 LLT PtrTy = MRI.getType(PtrReg); in legalizeLoad()
3134 auto Cast = B.buildAddrSpaceCast(ConstPtr, PtrReg); in legalizeLoad()
3186 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
3194 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
3199 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
3256 Register PtrReg = MI.getOperand(1).getReg(); in legalizeAtomicCmpXChg() local
3260 assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) && in legalizeAtomicCmpXChg()
3270 .addUse(PtrReg) in legalizeAtomicCmpXChg()
H A DAMDGPUInstructionSelector.cpp5303 Register PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm32() local
5310 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVISelLowering.cpp237 Register PtrReg = I.getOperand(0).getReg(); in validateLifetimeStart() local
239 Register PtrTypeReg = getTypeReg(MRI, PtrReg); in validateLifetimeStart()
254 doInsertBitcast(STI, MRI, GR, I, PtrReg, 0, NewPtrType); in validateLifetimeStart()
H A DSPIRVGlobalRegistry.h325 unsigned getPointeeTypeOp(Register PtrReg);
H A DSPIRVGlobalRegistry.cpp1317 unsigned SPIRVGlobalRegistry::getPointeeTypeOp(Register PtrReg) { in getPointeeTypeOp() argument
1318 SPIRVType *ElemType = getPointeeType(getSPIRVTypeForVReg(PtrReg)); in getPointeeTypeOp()
H A DSPIRVInstructionSelector.cpp3155 Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 1).getReg(); in selectIntrinsic() local
3165 .addUse(PtrReg) in selectIntrinsic()
3174 Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 2).getReg(); in selectIntrinsic() local
3178 .addUse(PtrReg) in selectIntrinsic()
H A DSPIRVBuiltins.cpp882 Register PtrReg = Call->Arguments[0]; in buildAtomicFloatingRMWInst() local
889 .addUse(PtrReg) in buildAtomicFloatingRMWInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp758 Register PtrReg = MI.getOperand(0).getReg(); in legalizeBRJT() local
759 LLT PtrTy = MRI.getType(PtrReg); in legalizeBRJT()
769 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, PtrReg, IndexReg); in legalizeBRJT()
786 TargetReg = MIRBuilder.buildPtrAdd(PtrTy, PtrReg, Load).getReg(0); in legalizeBRJT()
H A DRISCVInstructionSelector.cpp853 Register PtrReg = Op.getReg(); in replacePtrWithInt() local
854 assert(MRI->getType(PtrReg).isPointer() && "Operand is not a pointer!"); in replacePtrWithInt()
857 auto PtrToInt = MIB.buildPtrToInt(sXLen, PtrReg); in replacePtrWithInt()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1639 Register PtrReg = LoadMI.getPointerReg(); in narrowScalar() local
1646 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in narrowScalar()
1648 MIRBuilder.buildLoadInstr(LoadMI.getOpcode(), TmpReg, PtrReg, MMO); in narrowScalar()
4049 Register PtrReg = LoadMI.getPointerReg(); in lowerLoad() local
4079 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); in lowerLoad()
4082 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); in lowerLoad()
4087 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO); in lowerLoad()
4147 auto NewLoad = MIRBuilder.buildLoad(MoreTy, PtrReg, *NewMMO); in lowerLoad()
4164 LLT PtrTy = MRI.getType(PtrReg); in lowerLoad()
4168 PtrReg, *LargeMMO); in lowerLoad()
[all …]
H A DCombinerHelper.cpp986 Register PtrReg = LoadMI->getPointerReg(); in matchCombineLoadWithAndMask() local
1019 {TargetOpcode::G_ZEXTLOAD, {RegTy, MRI.getType(PtrReg)}, {MemDesc}})) in matchCombineLoadWithAndMask()
1027 B.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, Dst, PtrReg, *NewMMO); in matchCombineLoadWithAndMask()
2537 MachineInstr &MI, std::pair<Register, bool> &PtrReg) const { in matchCombineAddP2IToPtrAdd()
2545 PtrReg.second = false; in matchCombineAddP2IToPtrAdd()
2547 if (mi_match(SrcReg, MRI, m_GPtrToInt(m_Reg(PtrReg.first)))) { in matchCombineAddP2IToPtrAdd()
2550 LLT PtrTy = MRI.getType(PtrReg.first); in matchCombineAddP2IToPtrAdd()
2555 PtrReg.second = true; in matchCombineAddP2IToPtrAdd()
2562 MachineInstr &MI, std::pair<Register, bool> &PtrReg) const { in applyCombineAddP2IToPtrAdd()
2567 const bool DoCommute = PtrReg.second; in applyCombineAddP2IToPtrAdd()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp1107 Register PtrReg = LoadMI->getPointerReg(); in select() local
1108 MachineInstr *Ptr = MRI.getVRegDef(PtrReg); in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp13095 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
13157 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitPartwordAtomicBinary()
13162 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
13183 .addReg(PtrReg); in EmitPartwordAtomicBinary()
13226 .addReg(PtrReg); in EmitPartwordAtomicBinary()
14112 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
14181 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitInstrWithCustomInserter()
14186 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
14218 .addReg(PtrReg); in EmitInstrWithCustomInserter()
14242 .addReg(PtrReg); in EmitInstrWithCustomInserter()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp5271 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; in Select() local
5272 SDValue Chain = CurDAG->getCopyToReg(Node->getOperand(0), dl, PtrReg, in Select()