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Searched refs:PtrReg (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp333 Register PtrReg = Store.getPointerReg(); in applySplitStoreZero128() local
335 auto HighPtr = B.buildPtrAdd(MRI.getType(PtrReg), PtrReg, in applySplitStoreZero128()
340 B.buildStore(Zero, PtrReg, *LowMMO); in applySplitStoreZero128()
727 Register PtrReg = St->getPointerReg(); in optimizeConsecutiveMemOpAddressing() local
729 PtrReg, MRI, in optimizeConsecutiveMemOpAddressing()
731 GPtrAdd *PtrAdd = cast<GPtrAdd>(MRI.getVRegDef(PtrReg)); in optimizeConsecutiveMemOpAddressing()
H A DAArch64InstructionSelector.cpp2924 const Register PtrReg = LdSt.getPointerReg(); in select() local
2925 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); in select()
2929 assert(MRI.getType(PtrReg).isPointer() && in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp430 Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy); in lowerParameter() local
431 lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]); in lowerParameter()
450 B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO); in lowerParameter()
561 Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy); in lowerFormalArgumentsKernel() local
562 lowerParameterPtr(PtrReg, B, ArgOffset); in lowerFormalArgumentsKernel()
564 B.buildAddrSpaceCast(VRegs[i][0], PtrReg); in lowerFormalArgumentsKernel()
H A DAMDGPURegisterBankInfo.cpp1089 Register PtrReg = MI.getOperand(1).getReg(); in applyMappingLoad() local
1099 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1103 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1107 B.buildLoadFromOffset(MI.getOperand(0), PtrReg, *MMO, 0); in applyMappingLoad()
1121 auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0); in applyMappingLoad()
3431 Register PtrReg = MI.getOperand(0).getReg(); in applyMappingImpl() local
3432 unsigned PtrBank = getRegBankID(PtrReg, MRI, AMDGPU::SGPRRegBankID); in applyMappingImpl()
3437 unsigned AS = MRI.getType(PtrReg).getAddressSpace(); in applyMappingImpl()
3628 Register PtrReg) const { in getValueMappingForPtr()
3629 LLT PtrTy = MRI.getType(PtrReg); in getValueMappingForPtr()
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H A DAMDGPULegalizerInfo.cpp3070 Register PtrReg = MI.getOperand(1).getReg(); in legalizeLoad() local
3071 LLT PtrTy = MRI.getType(PtrReg); in legalizeLoad()
3076 auto Cast = B.buildAddrSpaceCast(ConstPtr, PtrReg); in legalizeLoad()
3128 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
3136 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
3141 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
3198 Register PtrReg = MI.getOperand(1).getReg(); in legalizeAtomicCmpXChg() local
3202 assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) && in legalizeAtomicCmpXChg()
3212 .addUse(PtrReg) in legalizeAtomicCmpXChg()
H A DAMDGPUInstructionSelector.cpp4269 Register PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm32() local
4276 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp759 Register PtrReg = Op.getReg(); in replacePtrWithInt() local
760 assert(MRI.getType(PtrReg).isPointer() && "Operand is not a pointer!"); in replacePtrWithInt()
763 auto PtrToInt = MIB.buildPtrToInt(sXLen, PtrReg); in replacePtrWithInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.h312 unsigned getPointeeTypeOp(Register PtrReg);
H A DSPIRVGlobalRegistry.cpp1079 unsigned SPIRVGlobalRegistry::getPointeeTypeOp(Register PtrReg) { in getPointeeTypeOp() argument
1080 SPIRVType *ElemType = getPointeeType(getSPIRVTypeForVReg(PtrReg)); in getPointeeTypeOp()
H A DSPIRVInstructionSelector.cpp2069 Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 2).getReg(); in selectIntrinsic() local
2070 unsigned PonteeOpType = GR.getPointeeTypeOp(PtrReg); in selectIntrinsic()
2074 BuildMI(BB, I, I.getDebugLoc(), TII.get(Op)).addUse(PtrReg).addImm(Size); in selectIntrinsic()
H A DSPIRVBuiltins.cpp851 Register PtrReg = Call->Arguments[0]; in buildAtomicFloatingRMWInst() local
852 MRI->setRegClass(PtrReg, &SPIRV::IDRegClass); in buildAtomicFloatingRMWInst()
866 .addUse(PtrReg) in buildAtomicFloatingRMWInst()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1376 Register PtrReg = LoadMI.getPointerReg(); in narrowScalar() local
1383 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in narrowScalar()
1385 MIRBuilder.buildLoadInstr(LoadMI.getOpcode(), TmpReg, PtrReg, MMO); in narrowScalar()
3472 Register PtrReg = LoadMI.getPointerReg(); in lowerLoad() local
3502 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); in lowerLoad()
3505 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); in lowerLoad()
3510 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO); in lowerLoad()
3572 LLT PtrTy = MRI.getType(PtrReg); in lowerLoad()
3576 PtrReg, *LargeMMO); in lowerLoad()
3581 auto SmallPtr = MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); in lowerLoad()
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H A DCombinerHelper.cpp921 Register PtrReg = LoadMI->getPointerReg(); in matchCombineLoadWithAndMask() local
954 {TargetOpcode::G_ZEXTLOAD, {RegTy, MRI.getType(PtrReg)}, {MemDesc}})) in matchCombineLoadWithAndMask()
962 B.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, Dst, PtrReg, *NewMMO); in matchCombineLoadWithAndMask()
2433 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in matchCombineAddP2IToPtrAdd() argument
2441 PtrReg.second = false; in matchCombineAddP2IToPtrAdd()
2443 if (mi_match(SrcReg, MRI, m_GPtrToInt(m_Reg(PtrReg.first)))) { in matchCombineAddP2IToPtrAdd()
2446 LLT PtrTy = MRI.getType(PtrReg.first); in matchCombineAddP2IToPtrAdd()
2451 PtrReg.second = true; in matchCombineAddP2IToPtrAdd()
2458 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in applyCombineAddP2IToPtrAdd() argument
2463 const bool DoCommute = PtrReg.second; in applyCombineAddP2IToPtrAdd()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp12267 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
12329 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitPartwordAtomicBinary()
12334 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
12355 .addReg(PtrReg); in EmitPartwordAtomicBinary()
12398 .addReg(PtrReg); in EmitPartwordAtomicBinary()
13279 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
13348 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitInstrWithCustomInserter()
13353 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
13385 .addReg(PtrReg); in EmitInstrWithCustomInserter()
13409 .addReg(PtrReg); in EmitInstrWithCustomInserter()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp5184 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; in Select() local
5185 SDValue Chain = CurDAG->getCopyToReg(Node->getOperand(0), dl, PtrReg, in Select()