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Searched refs:Pseudos (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td21 // TODO: Provide variants for MOV32/64imm Pseudos that dynamically
H A DSVEInstrFormats.td789 // Pseudos for destructive operands
815 // Pseudos for passthru operands
H A DAArch64InstrInfo.td1993 // Pseudos
10930 // Pseudos for codegen
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrCompiler.td1 //===-- M68kInstrCompiler.td - Pseudos and Patterns --------*- tablegen -*-===//
H A DM68kInstrData.td551 // Pseudos
582 // These Pseudos handle loading immediates to registers.
598 /// This group of Pseudos is analogues to the real x86 extending moves, but
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoSFB.td1 //===-- RISCVInstrInfoSFB.td - Pseudos for SFB -------------*- tablegen -*-===//
H A DRISCVInstrInfoVPseudos.td1 //===-- RISCVInstrInfoVPseudos.td - RISC-V 'V' Pseudos -----*- tablegen -*-===//
6109 // Pseudos.
6137 // Pseudos Unit-Stride Loads and Stores
H A DRISCVInstrInfo.td1932 // Pseudos if that extension is present.
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenSchedule.cpp82 ArrayRef<const CodeGenInstruction *> Pseudos = in apply() local
158 std::equal_range(Pseudos.begin(), Pseudos.end(), Prefix, Comp()); in apply()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td1106 // Pseudos.
1278 // Pseudos.
1284 // Pseudos for loading and storing ccond field of DSP control register.
H A DMipsMSAInstrInfo.td3683 // Pseudos used to implement BNZ.df, and BZ.df
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPseudo.td562 // Pseudos for circular buffer instructions. These are needed in order to
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57.td139 // Pseudos
163 // Pseudos
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZEC12.td12 // Pseudos expanded right after isel do not need to be modelled here.
H A DSystemZScheduleZ196.td12 // Pseudos expanded right after isel do not need to be modelled here.
H A DSystemZScheduleZ13.td12 // Pseudos expanded right after isel do not need to be modelled here.
H A DSystemZScheduleZ17.td12 // Pseudos expanded right after isel do not need to be modelled here.
H A DSystemZScheduleZ15.td12 // Pseudos expanded right after isel do not need to be modelled here.
H A DSystemZScheduleZ14.td12 // Pseudos expanded right after isel do not need to be modelled here.
H A DSystemZScheduleZ16.td12 // Pseudos expanded right after isel do not need to be modelled here.
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrCompiler.td1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstructions.td735 // Pseudos for the llvm.amdgcn.cs.chain intrinsic.