Searched refs:PredOp (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/ |
| H A D | Hexagon.cpp | 212 const Expr *PredOp = E->getArg(0); in EmitHexagonBuiltinExpr() local 214 if (auto *Cast = dyn_cast<ImplicitCastExpr>(PredOp)) { in EmitHexagonBuiltinExpr() 216 PredOp = Cast->getSubExpr(); in EmitHexagonBuiltinExpr() 217 Ops.push_back(V2Q(EmitScalarExpr(PredOp))); in EmitHexagonBuiltinExpr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 212 unsigned DstSR, const MachineOperand &PredOp, bool PredSense, 223 const MachineOperand &PredOp, bool Cond, 629 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, in genCondTfrFor() argument 643 unsigned PredState = getRegState(PredOp) & ~RegState::Kill; in genCondTfrFor() 652 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor() 657 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor() 863 const MachineOperand &PredOp, bool Cond, in predicateAt() argument 892 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0, in predicateAt() 893 PredOp.getSubReg()); in predicateAt()
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| H A D | HexagonGenMux.cpp | 231 MachineOperand &PredOp = MI.getOperand(1); in genMuxInBlock() local 232 if (PredOp.isUndef()) in genMuxInBlock() 235 Register PR = PredOp.getReg(); in genMuxInBlock()
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| H A D | HexagonISelLowering.cpp | 1177 SDValue PredOp = Op.getOperand(0); in LowerVSELECT() local 1189 DAG.getSelect(dl, WideTy, PredOp, in LowerVSELECT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrCDE.td | 94 dag PredOp; // Input predicate operand 115 !con(params.Iops1, (ins imm_13b:$imm), params.PredOp), 131 !con(params.Iops2, (ins imm_9b:$imm), params.PredOp), 149 !con(params.Iops3, (ins imm_6b:$imm), params.PredOp), 191 let PredOp = !if(acc, (ins pred:$p), (ins));
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1813 auto PredOp = ICmp.getOperand(1); in selectCompareBranchFedByICmp() local 1814 emitIntegerCompare(ICmp.getOperand(2), ICmp.getOperand(3), PredOp, MIB); in selectCompareBranchFedByICmp() 1816 static_cast<CmpInst::Predicate>(PredOp.getPredicate())); in selectCompareBranchFedByICmp() 2508 auto &PredOp = Cmp->getOperand(1); in earlySelect() local 2509 auto Pred = static_cast<CmpInst::Predicate>(PredOp.getPredicate()); in earlySelect() 2514 /*RHS=*/Cmp->getOperand(3), PredOp, MIB); in earlySelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 1706 auto PredOp = PredIntr->getOperand(0); in tryCombineFromSVBoolBinOp() local 1707 auto PredOpTy = cast<VectorType>(PredOp->getType()); in tryCombineFromSVBoolBinOp() 1711 SmallVector<Value *> NarrowedBinOpArgs = {PredOp}; in tryCombineFromSVBoolBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 3633 MachineOperand &PredOp = Def->getOperand(1); in applyNotCmp() local 3635 (CmpInst::Predicate)PredOp.getPredicate()); in applyNotCmp() 3636 PredOp.setPredicate(NewP); in applyNotCmp()
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