Searched refs:PartialRes (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 9067 const auto appendResult = [&](SDValue PartialRes) { in expandIS_FPCLASS() argument
9068 if (PartialRes) { in expandIS_FPCLASS()
9070 Res = DAG.getNode(ISD::OR, DL, ResultVT, Res, PartialRes); in expandIS_FPCLASS()
9072 Res = PartialRes; in expandIS_FPCLASS()
9094 SDValue PartialRes; in expandIS_FPCLASS() local
9101 PartialRes = DAG.getSetCC(DL, ResultVT, AbsV, ExpMaskV, ISD::SETLT); in expandIS_FPCLASS()
9105 PartialRes = DAG.getSetCC(DL, ResultVT, OpAsInt, ExpMaskV, ISD::SETULT); in expandIS_FPCLASS()
9109 PartialRes = DAG.getSetCC(DL, ResultVT, AbsV, ExpMaskV, ISD::SETLT); in expandIS_FPCLASS()
9110 PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, SignV); in expandIS_FPCLASS()
9113 appendResult(PartialRes); in expandIS_FPCLASS()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 5612 SmallVector<Register, 4> PartialRes; in legalizeLaneOp() local
5632 PartialRes.push_back(createLaneOp(Src0, Src1, Src2, PartialResTy)); in legalizeLaneOp()
5637 LLT::scalar(Ty.getSizeInBits()), PartialRes)); in legalizeLaneOp()
5639 B.buildMergeLikeInstr(DstReg, PartialRes); in legalizeLaneOp()
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