Searched refs:PartialRes (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 8662 const auto appendResult = [&](SDValue PartialRes) { in expandIS_FPCLASS() argument
8663 if (PartialRes) { in expandIS_FPCLASS()
8665 Res = DAG.getNode(ISD::OR, DL, ResultVT, Res, PartialRes); in expandIS_FPCLASS()
8667 Res = PartialRes; in expandIS_FPCLASS()
8689 SDValue PartialRes; in expandIS_FPCLASS() local
8696 PartialRes = DAG.getSetCC(DL, ResultVT, AbsV, ExpMaskV, ISD::SETLT); in expandIS_FPCLASS()
8700 PartialRes = DAG.getSetCC(DL, ResultVT, OpAsInt, ExpMaskV, ISD::SETULT); in expandIS_FPCLASS()
8704 PartialRes = DAG.getSetCC(DL, ResultVT, AbsV, ExpMaskV, ISD::SETLT); in expandIS_FPCLASS()
8705 PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, SignV); in expandIS_FPCLASS()
8708 appendResult(PartialRes); in expandIS_FPCLASS()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 5511 SmallVector<Register, 2> PartialRes; in legalizeLaneOp() local
5531 PartialRes.push_back(createLaneOp(Src0, Src1, Src2, PartialResTy)); in legalizeLaneOp()
5534 B.buildMergeLikeInstr(DstReg, PartialRes); in legalizeLaneOp()
|