| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 155 MVT PartVT, EVT ValueVT, const Value *V,
166 unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
173 PartVT, ValueVT, CC)) in getCopyFromParts()
177 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
186 unsigned PartBits = PartVT.getSizeInBits(); in getCopyFromParts()
199 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, PartVT, HalfVT, V, in getCopyFromParts()
202 PartVT, HalfVT, V, InChain); in getCopyFromParts()
217 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT, in getCopyFromParts()
233 } else if (PartVT.isFloatingPoint()) { in getCopyFromParts()
235 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
[all …]
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| H A D | LegalizeVectorTypes.cpp | 6021 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in WidenVecRes_EXTRACT_SUBVECTOR() local
6024 if (getTypeAction(PartVT) != TargetLowering::TypeWidenVector) { in WidenVecRes_EXTRACT_SUBVECTOR()
6029 DAG.getExtractSubvector(dl, PartVT, InOp, IdxVal + I * GCD)); in WidenVecRes_EXTRACT_SUBVECTOR()
6031 Parts.push_back(DAG.getUNDEF(PartVT)); in WidenVecRes_EXTRACT_SUBVECTOR()
6670 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in WidenVecRes_VECTOR_REVERSE() local
6678 DAG.getExtractSubvector(dl, PartVT, ReverseVal, IdxVal + i * GCD)); in WidenVecRes_VECTOR_REVERSE()
6680 Parts.push_back(DAG.getUNDEF(PartVT)); in WidenVecRes_VECTOR_REVERSE()
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| H A D | LegalizeDAG.cpp | 1504 EVT PartVT = Part.getValueType(); in ExpandInsertToVectorThroughStack() local
1519 Type *PartTy = PartVT.getTypeForEVT(*DAG.getContext()); in ExpandInsertToVectorThroughStack()
1523 if (PartVT.isVector()) { in ExpandInsertToVectorThroughStack()
1525 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, PartVT, Idx); in ExpandInsertToVectorThroughStack()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1648 EVT PartVT = VT; in getVectorTypeBreakdown() local
1651 LK = getTypeConversion(Context, PartVT); in getVectorTypeBreakdown()
1652 PartVT = LK.second; in getVectorTypeBreakdown()
1655 if (!PartVT.isVector()) { in getVectorTypeBreakdown()
1662 PartVT.getVectorElementCount().getKnownMinValue()); in getVectorTypeBreakdown()
1663 IntermediateVT = PartVT; in getVectorTypeBreakdown()
1759 MVT PartVT = in GetReturnInfo() local
1774 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.h | 416 SDValue *Parts, unsigned NumParts, MVT PartVT,
422 MVT PartVT, EVT ValueVT,
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| H A D | LoongArchISelLowering.cpp | 7436 EVT PartVT = PartValue.getValueType(); in LowerCall() local
7438 StoredSize += PartVT.getStoreSize(); in LowerCall()
7439 StackAlign = std::max(StackAlign, getPrefTypeAlign(PartVT, DAG)); in LowerCall()
8481 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
8486 PartVT == MVT::f32) { in splitValueIntoRegisterParts()
8503 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
8507 PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 611 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
615 unsigned NumParts, MVT PartVT, EVT ValueVT,
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| H A D | SystemZISelLowering.cpp | 1907 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
1909 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in splitValueIntoRegisterParts()
1920 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1921 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in joinRegisterPartsIntoValue()
2285 MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT); in LowerCall() local
2287 SlotVT = EVT::getIntegerVT(Ctx, PartVT.getSizeInBits() * N); in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.h | 328 SDValue *Parts, unsigned NumParts, MVT PartVT,
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| H A D | NVPTXISelLowering.cpp | 3325 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 339 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
344 unsigned NumParts, MVT PartVT, EVT ValueVT,
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| H A D | RISCVISelLowering.cpp | 2392 MVT PartVT = TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT); in getRegisterTypeForCallingConv() local
2394 return PartVT; in getRegisterTypeForCallingConv()
22632 EVT PartVT = PartValue.getValueType(); in LowerCall() local
22633 if (PartVT.isScalableVector()) in LowerCall()
22635 StoredSize += PartVT.getStoreSize(); in LowerCall()
22636 StackAlign = std::max(StackAlign, getPrefTypeAlign(PartVT, DAG)); in LowerCall()
23921 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
23929 NumParts == 1 && PartVT == MVT::Untyped) { in splitValueIntoRegisterParts()
23937 Parts[0] = DAG.getNode(RISCVISD::BuildGPRPair, DL, PartVT, Lo, Hi); in splitValueIntoRegisterParts()
23942 PartVT == MVT::f32) { in splitValueIntoRegisterParts()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 937 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
942 unsigned NumParts, MVT PartVT, EVT ValueVT,
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| H A D | ARMISelLowering.cpp | 4533 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
4535 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
4537 unsigned PartBits = PartVT.getSizeInBits(); in splitValueIntoRegisterParts()
4540 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
4549 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4550 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
4552 unsigned PartBits = PartVT.getSizeInBits(); in joinRegisterPartsIntoValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 1186 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
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| H A D | PPCISelLowering.cpp | 19476 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
19482 if (PartVT == MVT::f64 && in splitValueIntoRegisterParts()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 4629 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
4654 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 808 MVT PartVT = MVT::getVectorVT(VecTy.getVectorElementType(), OpsPerWord); in buildHvxVectorReg() local
810 SDValue W = buildVector32(Values.slice(i, OpsPerWord), dl, PartVT, DAG); in buildHvxVectorReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 8102 EVT PartVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2); in lowerBUILD_VECTOR() local
8103 MVT PartIntVT = MVT::getIntegerVT(PartVT.getSizeInBits()); in lowerBUILD_VECTOR()
8108 PartVT, SL, {Op.getOperand(P * 2), Op.getOperand(P * 2 + 1)}); in lowerBUILD_VECTOR()
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