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Searched refs:PartVT (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp159 MVT PartVT, EVT ValueVT, const Value *V,
170 unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
177 PartVT, ValueVT, CC)) in getCopyFromParts()
181 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
190 unsigned PartBits = PartVT.getSizeInBits(); in getCopyFromParts()
203 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, PartVT, HalfVT, V, in getCopyFromParts()
206 PartVT, HalfVT, V, InChain); in getCopyFromParts()
221 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT, in getCopyFromParts()
237 } else if (PartVT.isFloatingPoint()) { in getCopyFromParts()
239 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
[all …]
H A DLegalizeVectorTypes.cpp5602 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in WidenVecRes_EXTRACT_SUBVECTOR() local
5605 if (getTypeAction(PartVT) != TargetLowering::TypeWidenVector) { in WidenVecRes_EXTRACT_SUBVECTOR()
5610 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, PartVT, InOp, in WidenVecRes_EXTRACT_SUBVECTOR()
5613 Parts.push_back(DAG.getUNDEF(PartVT)); in WidenVecRes_EXTRACT_SUBVECTOR()
6226 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in WidenVecRes_VECTOR_REVERSE() local
6234 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, PartVT, ReverseVal, in WidenVecRes_VECTOR_REVERSE()
6237 Parts.push_back(DAG.getUNDEF(PartVT)); in WidenVecRes_VECTOR_REVERSE()
H A DLegalizeDAG.cpp1470 EVT PartVT = Part.getValueType(); in ExpandInsertToVectorThroughStack() local
1483 if (PartVT.isVector()) { in ExpandInsertToVectorThroughStack()
1485 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, PartVT, Idx); in ExpandInsertToVectorThroughStack()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1549 EVT PartVT = VT; in getVectorTypeBreakdown() local
1552 LK = getTypeConversion(Context, PartVT); in getVectorTypeBreakdown()
1553 PartVT = LK.second; in getVectorTypeBreakdown()
1556 if (!PartVT.isVector()) { in getVectorTypeBreakdown()
1563 PartVT.getVectorElementCount().getKnownMinValue()); in getVectorTypeBreakdown()
1564 IntermediateVT = PartVT; in getVectorTypeBreakdown()
1661 MVT PartVT = in GetReturnInfo() local
1683 ISD::OutputArg(OutFlags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h592 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
596 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DSystemZISelLowering.cpp1579 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
1581 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in splitValueIntoRegisterParts()
1592 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1593 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in joinRegisterPartsIntoValue()
1947 MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT); in LowerCall() local
1949 SlotVT = EVT::getIntegerVT(Ctx, PartVT.getSizeInBits() * N); in LowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h911 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
916 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DARMISelLowering.cpp4463 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
4465 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
4467 unsigned PartBits = PartVT.getSizeInBits(); in splitValueIntoRegisterParts()
4470 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
4479 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4480 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
4482 unsigned PartBits = PartVT.getSizeInBits(); in joinRegisterPartsIntoValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h787 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
792 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DRISCVISelLowering.cpp2347 MVT PartVT = TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT); in getRegisterTypeForCallingConv() local
2349 if (RV64LegalI32 && Subtarget.is64Bit() && PartVT == MVT::i32) in getRegisterTypeForCallingConv()
2352 return PartVT; in getRegisterTypeForCallingConv()
20026 EVT PartVT = PartValue.getValueType(); in LowerCall() local
20027 if (PartVT.isScalableVector()) in LowerCall()
20029 StoredSize += PartVT.getStoreSize(); in LowerCall()
20030 StackAlign = std::max(StackAlign, getPrefTypeAlign(PartVT, DAG)); in LowerCall()
21477 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
21481 PartVT == MVT::f32) { in splitValueIntoRegisterParts()
21493 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.h648 SDValue *Parts, unsigned NumParts, MVT PartVT,
H A DNVPTXISelLowering.cpp3145 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h1169 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
H A DPPCISelLowering.cpp18474 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
18480 if (PartVT == MVT::f64 && in splitValueIntoRegisterParts()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4454 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
4479 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp5360 EVT PartVT = PartValue.getValueType(); in LowerCall() local
5362 StoredSize += PartVT.getStoreSize(); in LowerCall()
5363 StackAlign = std::max(StackAlign, getPrefTypeAlign(PartVT, DAG)); in LowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp798 MVT PartVT = MVT::getVectorVT(VecTy.getVectorElementType(), OpsPerWord); in buildHvxVectorReg() local
800 SDValue W = buildVector32(Values.slice(i, OpsPerWord), dl, PartVT, DAG); in buildHvxVectorReg()