Home
last modified time | relevance | path

Searched refs:ParentA (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanAnalysis.cpp368 const VPBlockBase *ParentA = A->getParent(); in properlyDominates() local
370 if (ParentA == ParentB) in properlyDominates()
391 return Base::properlyDominates(ParentA, ParentB); in properlyDominates()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DReachingDefAnalysis.cpp380 MachineBasicBlock *ParentA = A->getParent(); in hasSameReachingDef() local
382 if (ParentA != ParentB) in hasSameReachingDef()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp604 bool matchVPTERNLOG(SDNode *Root, SDNode *ParentA, SDNode *ParentB,
4587 bool X86DAGToDAGISel::matchVPTERNLOG(SDNode *Root, SDNode *ParentA, in matchVPTERNLOG() argument
4591 assert(A.isOperandOf(ParentA) && B.isOperandOf(ParentB) && in matchVPTERNLOG()
4622 } else if (tryFoldLoadOrBCast(Root, ParentA, A, Tmp0, Tmp1, Tmp2, Tmp3, in matchVPTERNLOG()
4753 SDNode *ParentA = N; in tryVPTERNLOG() local
4775 PeekThroughNot(A, ParentA, TernlogMagicA); in tryVPTERNLOG()
4801 return matchVPTERNLOG(N, ParentA, ParentB, ParentC, A, B, C, Imm); in tryVPTERNLOG()