Searched refs:PairVT (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 15307 EVT PairVT = SubVT.getDoubleNumVectorElementsVT(*DAG.getContext()); in LowerCONCAT_VECTORS() local
15309 DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), PairVT, V1, V2); in LowerCONCAT_VECTORS()
18465 EVT PairVT = ExtVT0.getDoubleNumVectorElementsVT(*DAG.getContext()); in performUADDVZextCombine() local
18467 DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(A), PairVT, Ext0, Ext1); in performUADDVZextCombine()
29462 EVT PairVT = SrcVT.getDoubleNumVectorElementsVT(*DAG.getContext()); in LowerFixedLengthConcatVectorsToSVE() local
29464 Ops.push_back(DAG.getNode(ISD::CONCAT_VECTORS, DL, PairVT, in LowerFixedLengthConcatVectorsToSVE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 23925 MVT PairVT = Subtarget.is64Bit() ? MVT::i128 : MVT::i64; in splitValueIntoRegisterParts() local
23926 if ((ValueVT == PairVT || in splitValueIntoRegisterParts()
24014 MVT PairVT = Subtarget.is64Bit() ? MVT::i128 : MVT::i64; in joinRegisterPartsIntoValue() local
24015 if ((ValueVT == PairVT || in joinRegisterPartsIntoValue()
24027 Val = DAG.getNode(ISD::BUILD_PAIR, DL, PairVT, Val.getValue(0), in joinRegisterPartsIntoValue()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 21963 EVT PairVT = EVT::getIntegerVT(Context, ElementSizeBytes * 8 * 2); in tryStoreMergeOfLoads() local
21965 (hasOperation(ISD::ROTL, PairVT) || in tryStoreMergeOfLoads()
21966 hasOperation(ISD::ROTR, PairVT))) { in tryStoreMergeOfLoads()
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