Searched refs:PTRUE (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 81 PTRUE, enumerator
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| H A D | HexagonISelLowering.cpp | 1966 case HexagonISD::PTRUE: return "HexagonISD::PTRUE"; in getTargetNodeName()
2995 return DAG.getNode(HexagonISD::PTRUE, dl, VecTy); in LowerBUILD_VECTOR()
3525 case HexagonISD::PTRUE: in PerformDAGCombine()
3539 if (C1->getOpcode() == HexagonISD::PTRUE) { in PerformDAGCombine()
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| H A D | HexagonPatterns.td | 96 def HexagonPTRUE: SDNode<"HexagonISD::PTRUE", SDTVecLeaf>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 295 case AArch64ISD::PTRUE: in isZeroingInactiveLanes()
5512 return DAG.getNode(AArch64ISD::PTRUE, DL, VT, in getPTrue()
14510 if (N.getOpcode() == AArch64ISD::PTRUE && in isAllActivePredicate()
14516 if (N.getOpcode() == AArch64ISD::PTRUE) { in isAllActivePredicate()
23048 SDValue(MLD, 0).hasOneUse() && Mask->getOpcode() == AArch64ISD::PTRUE && in performUnpackCombine()
24136 MST->isUnindexed() && Mask->getOpcode() == AArch64ISD::PTRUE && in performMSTORECombine()
25390 if (Pred.getOpcode() == AArch64ISD::PTRUE && in performSetCCPunpkCombine()
25391 InnerPred.getOpcode() == AArch64ISD::PTRUE && in performSetCCPunpkCombine()
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| H A D | SVEInstrFormats.td | 466 def AArch64ptrue : SDNode<"AArch64ISD::PTRUE", SDT_AArch64PTrue>;
469 defm PTRUE : sve_int_ptrue<0b000, "ptrue", AArch64ptrue>;
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