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Searched refs:PRE_INC (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1523 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
H A DBasicTTIImpl.h198 return ISD::PRE_INC; in getISDIndexedMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp209 if (N->getAddressingMode() == ISD::PRE_INC) { in matchLSNode()
H A DSelectionDAGDumper.cpp567 case ISD::PRE_INC: return "<pre-inc>"; in getIndexedModeName()
H A DDAGCombiner.cpp18455 if (!getCombineLoadStoreParts(N, ISD::PRE_INC, ISD::PRE_DEC, IsLoad, IsMasked, in CombineToPreIndexedLoadStore()
18824 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB); in SplitIndexingFromLoad()
28266 Offset = (LSN->getAddressingMode() == ISD::PRE_INC) ? C->getSExtValue() in mayAlias()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp842 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg()
878 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre()
898 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm()
977 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode3Offset()
1406 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm8Offset()
1475 ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm7Offset()
1603 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryARMIndexedLoad()
1710 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryT2IndexedLoad()
1774 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
1790 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
H A DARMISelLowering.cpp326 for (unsigned im = (unsigned)ISD::PRE_INC; in addMVEVectorTypes()
356 for (unsigned im = (unsigned)ISD::PRE_INC; in addMVEVectorTypes()
440 for (unsigned im = (unsigned)ISD::PRE_INC; in addMVEVectorTypes()
1125 for (unsigned im = (unsigned)ISD::PRE_INC; in ARMTargetLowering()
19979 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; in getPreIndexedAddressParts()
H A DARMInstrMVE.td7117 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
7201 return cast<MaskedStoreSDNode>(N)->isTruncatingStore() && (AM == ISD::PRE_INC || AM == ISD::PRE_DEC);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp679 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()
700 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp233 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
234 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
235 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
236 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
237 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
238 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
239 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
240 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
241 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
242 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
[all …]
H A DPPCISelDAGToDAG.cpp5545 ST->getAddressingMode() != ISD::PRE_INC) in Select()
5556 if (LD->getAddressingMode() != ISD::PRE_INC) { in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp764 assert((AM == ISD::PRE_INC || AM == ISD::POST_INC) && in tryIndexedLoad()
766 bool IsPre = AM == ISD::PRE_INC; in tryIndexedLoad()
H A DRISCVISelLowering.cpp1428 for (unsigned im : {ISD::PRE_INC, ISD::POST_INC}) { in RISCVTargetLowering()
21242 AM = ISD::PRE_INC;
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td1341 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1352 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1584 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad()
H A DAArch64ISelLowering.cpp1053 for (unsigned im = (unsigned)ISD::PRE_INC; in AArch64TargetLowering()
1941 for (unsigned im = (unsigned)ISD::PRE_INC; in addTypeForNEON()
25728 AM = ISD::PRE_INC; in getPreIndexedAddressParts()