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Searched refs:PRE_DEC (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp214 } else if (N->getAddressingMode() == ISD::PRE_DEC) { in matchLSNode()
247 if (LSBase->getAddressingMode() == ISD::PRE_DEC || in matchLSNode()
H A DSelectionDAGDumper.cpp568 case ISD::PRE_DEC: return "<pre-dec>"; in getIndexedModeName()
H A DDAGCombiner.cpp18455 if (!getCombineLoadStoreParts(N, ISD::PRE_INC, ISD::PRE_DEC, IsLoad, IsMasked, in CombineToPreIndexedLoadStore()
18635 int X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1; in CombineToPreIndexedLoadStore()
18636 int Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1; in CombineToPreIndexedLoadStore()
28267 : (LSN->getAddressingMode() == ISD::PRE_DEC) in mayAlias()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp150 (AM != ISD::POST_INC && AM != ISD::PRE_DEC)) { in selectIndexedLoad()
156 bool isPre = (AM == ISD::PRE_DEC); in selectIndexedLoad()
H A DAVRISelLowering.cpp125 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
126 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
129 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
130 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
1116 AM = ISD::PRE_DEC; in getPreIndexedAddressParts()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1523 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
H A DBasicTTIImpl.h200 return ISD::PRE_DEC; in getISDIndexedMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1603 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryARMIndexedLoad()
1710 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryT2IndexedLoad()
1774 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
1790 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
H A DARMInstrMVE.td7117 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
7201 return cast<MaskedStoreSDNode>(N)->isTruncatingStore() && (AM == ISD::PRE_INC || AM == ISD::PRE_DEC);
H A DARMISelLowering.cpp19979 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; in getPreIndexedAddressParts()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td1341 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1352 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1584 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad()