Searched refs:PPRRegClass (Results 1 – 6 of 6) sorted by relevance
2994 else if (AArch64::PPRRegClass.contains(RPI.Reg1)) in computeCalleeSaveRegisterPairs()3593 AArch64::PPRRegClass.contains(Reg); in determineStackHazardSlot()3719 if (AArch64::PPRRegClass.contains(Reg) || in determineCalleeSaves()4000 AArch64::PPRRegClass.contains(CS.getReg())) { in getSVECalleeSaveSlotRange()5128 if (AArch64::PPRRegClass.contains(MI.getOperand(0).getReg())) in emitRemarks()
54 if (AArch64::PPRRegClass.contains(Reg)) in regNeedsCFI()
1113 } else if (AArch64::PPRRegClass.contains(Reg)) { in PrintAsmOperand()1114 RegClass = &AArch64::PPRRegClass; in PrintAsmOperand()
4512 if (AArch64::PPRRegClass.contains(DestReg) && in copyPhysReg()4513 AArch64::PPRRegClass.contains(SrcReg)) { in copyPhysReg()4854 AArch64::PPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()5026 else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
429 addRegisterClass(MVT::nxv1i1, &AArch64::PPRRegClass); in AArch64TargetLowering()430 addRegisterClass(MVT::nxv2i1, &AArch64::PPRRegClass); in AArch64TargetLowering()431 addRegisterClass(MVT::nxv4i1, &AArch64::PPRRegClass); in AArch64TargetLowering()432 addRegisterClass(MVT::nxv8i1, &AArch64::PPRRegClass); in AArch64TargetLowering()433 addRegisterClass(MVT::nxv16i1, &AArch64::PPRRegClass); in AArch64TargetLowering()464 addRegisterClass(MVT::aarch64svcount, &AArch64::PPRRegClass); in AArch64TargetLowering()7367 RC = &AArch64::PPRRegClass; in LowerFormalArguments()7370 RC = &AArch64::PPRRegClass; in LowerFormalArguments()8304 AArch64::PPRRegClass.contains(Loc.getLocReg()); in LowerCall()11496 : &AArch64::PPRRegClass; in getPredicateRegisterClass()
5290 auto PPRRegClass = AArch64MCRegisterClasses[AArch64::PPRRegClassID]; in validateInstruction() local5297 PPRRegClass.contains(Inst.getOperand(i).getReg())) { in validateInstruction()