Searched refs:PPRRegClass (Results 1 – 7 of 7) sorted by relevance
121 AArch64::PPRRegClass.contains(SR); in isSVERegOp()126 TRI.getCommonSubClass(&AArch64::PPRRegClass, RC); in isSVERegOp()
3284 } else if (AArch64::PPRRegClass.contains(RPI.Reg1)) { in computeCalleeSaveRegisterPairs()3286 RPI.RC = &AArch64::PPRRegClass; in computeCalleeSaveRegisterPairs()3892 AArch64::PPRRegClass.contains(Reg); in determineStackHazardSlot()4002 if (RegInfo->getSpillSize(AArch64::PPRRegClass) == 16 && in determineCalleeSaves()4059 if (AArch64::PPRRegClass.contains(Reg) || in determineCalleeSaves()4346 AArch64::PPRRegClass.contains(CS.getReg())) { in getSVECalleeSaveSlotRange()4727 if (AFI->hasStackFrame() && TRI.getSpillSize(AArch64::PPRRegClass) == 16) { in processFunctionBeforeFrameFinalized()5812 AArch64::PPRRegClass.contains(MI.getOperand(0).getReg())) { in emitRemarks()
55 if (AArch64::PPRRegClass.contains(Reg)) in regNeedsCFI()
5101 if (AArch64::PPRRegClass.contains(DestReg) && in copyPhysReg()5102 AArch64::PPRRegClass.contains(SrcReg)) { in copyPhysReg()5492 AArch64::PPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()5547 } else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()5675 else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()5732 } else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1224 } else if (AArch64::PPRRegClass.contains(Reg)) { in PrintAsmOperand()1225 RegClass = &AArch64::PPRRegClass; in PrintAsmOperand()
438 addRegisterClass(MVT::nxv1i1, &AArch64::PPRRegClass); in AArch64TargetLowering()439 addRegisterClass(MVT::nxv2i1, &AArch64::PPRRegClass); in AArch64TargetLowering()440 addRegisterClass(MVT::nxv4i1, &AArch64::PPRRegClass); in AArch64TargetLowering()441 addRegisterClass(MVT::nxv8i1, &AArch64::PPRRegClass); in AArch64TargetLowering()442 addRegisterClass(MVT::nxv16i1, &AArch64::PPRRegClass); in AArch64TargetLowering()473 addRegisterClass(MVT::aarch64svcount, &AArch64::PPRRegClass); in AArch64TargetLowering()7846 RC = &AArch64::PPRRegClass; in LowerFormalArguments()7849 RC = &AArch64::PPRRegClass; in LowerFormalArguments()8906 AArch64::PPRRegClass.contains(Loc.getLocReg()); in LowerCall()12325 return std::make_pair(AArch64::P0 + V, &AArch64::PPRRegClass); in parseSVERegAsConstraint()[all …]
5433 auto PPRRegClass = AArch64MCRegisterClasses[AArch64::PPRRegClassID]; in validateInstruction() local5440 PPRRegClass.contains(Inst.getOperand(i).getReg())) { in validateInstruction()