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Searched refs:PPC (Results 1 – 25 of 136) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCPredicates.cpp1 //===-- PPCPredicates.cpp - PPC Branch Predicate Information --------------===//
17 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
19 case PPC::PRED_EQ: return PPC::PRED_NE; in InvertPredicate()
20 case PPC::PRED_NE: return PPC::PRED_EQ; in InvertPredicate()
21 case PPC::PRED_LT: return PPC in InvertPredicate()
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H A DPPCELFObjectWriter.cpp46 case PPC::S_DTPMOD: in getRelocType()
47 case PPC::S_DTPREL: in getRelocType()
48 case PPC::S_DTPREL_HA: in getRelocType()
49 case PPC::S_DTPREL_HI: in getRelocType()
50 case PPC::S_DTPREL_HIGH: in getRelocType()
51 case PPC::S_DTPREL_HIGHA: in getRelocType()
52 case PPC::S_DTPREL_HIGHER: in getRelocType()
53 case PPC::S_DTPREL_HIGHERA: in getRelocType()
54 case PPC::S_DTPREL_HIGHEST: in getRelocType()
55 case PPC::S_DTPREL_HIGHESTA: in getRelocType()
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H A DPPCMCAsmInfo.cpp23 {PPC::S_DTPREL, "DTPREL"},
24 {PPC::S_GOT, "GOT"},
25 {PPC::S_GOT_HA, "got@ha"},
26 {PPC::S_GOT_HI, "got@h"},
27 {PPC::S_GOT_LO, "got@l"},
28 {PPC::S_HA, "ha"},
29 {PPC::S_HI, "h"},
30 {PPC::S_HIGH, "high"},
31 {PPC::S_HIGHA, "higha"},
32 {PPC::S_HIGHER, "higher"},
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H A DPPCMCCodeEmitter.cpp46 case PPC::fixup_ppc_br24: in addFixup()
47 case PPC::fixup_ppc_br24_notoc: in addFixup()
48 case PPC::fixup_ppc_brcond14: in addFixup()
49 case PPC::fixup_ppc_pcrel34: in addFixup()
67 (isNoTOCCallInstr(MI) ? PPC::fixup_ppc_br24_notoc : PPC::fixup_ppc_br24)); in getDirectBrEncoding()
84 case PPC::BL8_NOTOC: in isNoTOCCallInstr()
85 case PPC::BL8_NOTOC_TLS: in isNoTOCCallInstr()
86 case PPC::BL8_NOTOC_RM: in isNoTOCCallInstr()
89 case PPC::BL8: in isNoTOCCallInstr()
90 case PPC::BL: in isNoTOCCallInstr()
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H A DPPCMCTargetDesc.h17 #undef PPC
37 namespace PPC {
259 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
260 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
261 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
262 static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC::Fpair); \
263 static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
264 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
265 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
266 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
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H A DPPCInstPrinter.cpp64 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) && in printInst()
95 if (SymExpr && getSpecifier(SymExpr) == PPC::S_PCREL_OPT) { in printInst()
97 if (MI->getOpcode() == PPC::PLDpc) { in printInst()
115 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
138 if (MI->getOpcode() == PPC::RLDICR || in printInst()
139 MI->getOpcode() == PPC::RLDICR_32) { in printInst()
164 if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) && in printInst()
165 (!TT.isOSAIX() || STI.hasFeature(PPC::FeatureModernAIXAs))) { in printInst()
168 if (MI->getOpcode() == PPC::DCBTST) in printInst()
174 bool IsBookE = STI.hasFeature(PPC::FeatureBookE); in printInst()
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H A DPPCXCOFFObjectWriter.cpp59 case PPC::fixup_ppc_half16: { in getRelocTypeAndSignSize()
64 case PPC::S_None: in getRelocTypeAndSignSize()
66 case PPC::S_U: in getRelocTypeAndSignSize()
68 case PPC::S_L: in getRelocTypeAndSignSize()
70 case PPC::S_AIX_TLSLE: in getRelocTypeAndSignSize()
72 case PPC::S_AIX_TLSLD: in getRelocTypeAndSignSize()
76 case PPC::fixup_ppc_half16ds: in getRelocTypeAndSignSize()
77 case PPC::fixup_ppc_half16dq: { in getRelocTypeAndSignSize()
83 case PPC::S_None: in getRelocTypeAndSignSize()
85 case PPC::S_L: in getRelocTypeAndSignSize()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp91 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP, in PPCInstrInfo()
93 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
103 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
104 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
122 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
126 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
127 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
182 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
183 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
185 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
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H A DPPCRegisterInfo.cpp97 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, in PPCRegisterInfo()
101 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; in PPCRegisterInfo()
102 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; in PPCRegisterInfo()
103 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; in PPCRegisterInfo()
104 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
105 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; in PPCRegisterInfo()
106 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
107 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
108 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
109 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; in PPCRegisterInfo()
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H A DPPCInstrInfo.h105 #define NoInstr PPC::INSTRUCTION_LIST_END
107 {PPC::LWZ, \
108 PPC::LD, \
109 PPC::LFD, \
110 PPC::LFS, \
111 PPC::RESTORE_CR, \
112 PPC::RESTORE_CRBIT, \
113 PPC::LVX, \
114 PPC::LXVD2X, \
115 PPC::LXSDX, \
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H A DPPCVSXSwapRemoval.cpp165 return (isRegInClass(Reg, &PPC::VSRCRegClass) || in isVecReg()
166 isRegInClass(Reg, &PPC::VRRCRegClass)); in isVecReg()
171 return (isRegInClass(Reg, &PPC::VSFRCRegClass) || in isScalarVecReg()
172 isRegInClass(Reg, &PPC::VSSRCRegClass)); in isScalarVecReg()
286 case PPC::XXPERMDI: { in gatherVectorInstructions()
335 case PPC::LVX: in gatherVectorInstructions()
342 case PPC::LXVD2X: in gatherVectorInstructions()
343 case PPC::LXVW4X: in gatherVectorInstructions()
349 case PPC::LXSDX: in gatherVectorInstructions()
350 case PPC::LXSSPX: in gatherVectorInstructions()
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H A DPPCCallingConv.cpp33 static const MCPhysReg ELF64ArgGPRs[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6, in CC_PPC64_ELF_Shadow_GPR_Regs()
34 PPC::X7, PPC::X8, PPC::X9, PPC::X10}; in CC_PPC64_ELF_Shadow_GPR_Regs()
52 if ((State.AllocateReg(ELF64ArgGPRs) - PPC::X3) % 2 == 1) in CC_PPC64_ELF_Shadow_GPR_Regs()
72 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_AlignArgRegs()
73 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
97 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
98 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
122 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
123 PPC::F8 in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
132 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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H A DPPCRegisterInfo.h28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit()
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit()
30 Reg = PPC::CR0; in getCRFromCRBit()
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit()
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit()
33 Reg = PPC::CR1; in getCRFromCRBit()
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || in getCRFromCRBit()
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) in getCRFromCRBit()
36 Reg = PPC::CR2; in getCRFromCRBit()
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || in getCRFromCRBit()
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H A DPPCFastISel.cpp139 return RC->getID() == PPC::VSFRCRegClassID; in isVSFRCRegClass()
142 return RC->getID() == PPC::VSSRCRegClassID; in isVSSRCRegClass()
152 Register DestReg, const PPC::Predicate Pred);
155 unsigned FP64LoadOpc = PPC::LFD);
188 static std::optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) { in getComparePred()
220 return PPC::PRED_EQ; in getComparePred()
225 return PPC::PRED_GT; in getComparePred()
230 return PPC::PRED_GE; in getComparePred()
235 return PPC::PRED_LT; in getComparePred()
240 return PPC::PRED_LE; in getComparePred()
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H A DPPCFrameLowering.cpp98 {PPC::F31, -8}, \ in getCalleeSavedSpillSlots()
99 {PPC::F30, -16}, \ in getCalleeSavedSpillSlots()
100 {PPC::F29, -24}, \ in getCalleeSavedSpillSlots()
101 {PPC::F28, -32}, \ in getCalleeSavedSpillSlots()
102 {PPC::F27, -40}, \ in getCalleeSavedSpillSlots()
103 {PPC::F26, -48}, \ in getCalleeSavedSpillSlots()
104 {PPC::F25, -56}, \ in getCalleeSavedSpillSlots()
105 {PPC::F24, -64}, \ in getCalleeSavedSpillSlots()
106 {PPC::F23, -72}, \ in getCalleeSavedSpillSlots()
107 {PPC::F22, -80}, \ in getCalleeSavedSpillSlots()
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H A DPPCMIPeephole.cpp145 BuildMI(MBB, At, At->getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), Reg); in addDummyDef()
171 assert((MF.getRegInfo().use_empty(PPC::X2) || in runOnMachineFunction()
230 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || in getKnownLeadingZeroCount()
231 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec) in getKnownLeadingZeroCount()
234 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && in getKnownLeadingZeroCount()
238 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in getKnownLeadingZeroCount()
239 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || in getKnownLeadingZeroCount()
240 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in getKnownLeadingZeroCount()
244 if (Opcode == PPC::ANDI_rec) { in getKnownLeadingZeroCount()
249 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec || in getKnownLeadingZeroCount()
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H A DPPCTLSDynamicCall.cpp64 bool IsTLSTPRelMI = MI.getOpcode() == PPC::GETtlsTpointer32AIX; in processBlock()
65 bool IsTLSLDAIXMI = (MI.getOpcode() == PPC::TLSLDAIX8 || in processBlock()
66 MI.getOpcode() == PPC::TLSLDAIX); in processBlock()
68 if (MI.getOpcode() != PPC::ADDItlsgdLADDR && in processBlock()
69 MI.getOpcode() != PPC::ADDItlsldLADDR && in processBlock()
70 MI.getOpcode() != PPC::ADDItlsgdLADDR32 && in processBlock()
71 MI.getOpcode() != PPC::ADDItlsldLADDR32 && in processBlock()
72 MI.getOpcode() != PPC::TLSGDAIX && in processBlock()
73 MI.getOpcode() != PPC::TLSGDAIX8 && !IsTLSTPRelMI && !IsPCREL && in processBlock()
79 if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN) in processBlock()
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H A DPPCAsmPrinter.cpp112 static inline TOCKey getEmptyKey() { return {nullptr, PPC::S_None}; } in getEmptyKey()
114 return {(const MCSymbol *)1, PPC::S_None}; in getTombstoneKey()
179 PPCMCExpr::Specifier Kind = PPC::S_None);
332 O << PPC::stripRegisterPrefix(RegName); in printOperand()
392 if (PPC::isVRRegister(Reg)) in PrintAsmOperand()
393 Reg = PPC::VSX32 + (Reg - PPC::V0); in PrintAsmOperand()
394 else if (PPC::isVFRegister(Reg)) in PrintAsmOperand()
395 Reg = PPC::VSX32 + (Reg - PPC::VF0); in PrintAsmOperand()
398 RegName = PPC::stripRegisterPrefix(RegName); in PrintAsmOperand()
543 MII->getOpcode() == PPC::DBG_VALUE || in LowerSTACKMAP()
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H A DPPCExpandAtomicPseudoInsts.cpp52 const MCInstrDesc &OR = TII->get(PPC::OR8); in PairedCopy()
53 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy()
91 case PPC::ATOMIC_SWAP_I128: in expandMI()
92 case PPC::ATOMIC_LOAD_ADD_I128: in expandMI()
93 case PPC::ATOMIC_LOAD_SUB_I128: in expandMI()
94 case PPC::ATOMIC_LOAD_XOR_I128: in expandMI()
95 case PPC::ATOMIC_LOAD_NAND_I128: in expandMI()
96 case PPC::ATOMIC_LOAD_AND_I128: in expandMI()
97 case PPC::ATOMIC_LOAD_OR_I128: in expandMI()
99 case PPC::ATOMIC_CMP_SWAP_I128: in expandMI()
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H A DPPCPreEmitPeephole.cpp60 case PPC::LBZ: in hasPCRelativeForm()
61 case PPC::LBZ8: in hasPCRelativeForm()
62 case PPC::LHA: in hasPCRelativeForm()
63 case PPC::LHA8: in hasPCRelativeForm()
64 case PPC::LHZ: in hasPCRelativeForm()
65 case PPC::LHZ8: in hasPCRelativeForm()
66 case PPC::LWZ: in hasPCRelativeForm()
67 case PPC::LWZ8: in hasPCRelativeForm()
68 case PPC::STB: in hasPCRelativeForm()
69 case PPC::STB8: in hasPCRelativeForm()
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H A DPPCMCInstLower.cpp57 PPCMCExpr::Specifier RefKind = PPC::S_None; in GetSymbolRef()
63 RefKind = PPC::S_TPREL_LO; in GetSymbolRef()
66 RefKind = PPC::S_TPREL_HA; in GetSymbolRef()
69 RefKind = PPC::S_DTPREL_LO; in GetSymbolRef()
72 RefKind = PPC::S_GOT_TLSLD_LO; in GetSymbolRef()
75 RefKind = PPC::S_TOC_LO; in GetSymbolRef()
78 RefKind = PPC::S_TLS; in GetSymbolRef()
81 RefKind = PPC::S_TLS_PCREL; in GetSymbolRef()
90 RefKind = PPC::S_PLT; in GetSymbolRef()
92 RefKind = PPC::S_PCREL; in GetSymbolRef()
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H A DPPCISelDAGToDAG.cpp251 Align(4)) == PPC::AM_DSForm; in SelectDSForm()
259 Align(16)) == PPC::AM_DQForm; in SelectDQForm()
267 std::nullopt) == PPC::AM_DForm; in SelectDForm()
275 std::nullopt) == PPC::AM_PCRel; in SelectPCRelForm()
283 PPC::AM_PrefixDForm; in SelectPDForm()
290 std::nullopt) == PPC::AM_XForm; in SelectXForm()
298 PPC::AM_XForm; in SelectForceXForm()
476 GlobalBaseReg = PPC::R30; in INITIALIZE_PASS()
479 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR)); in INITIALIZE_PASS()
480 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in INITIALIZE_PASS()
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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaPPC.cpp60 case PPC::BI__builtin_divde: in isPPC_64Builtin()
61 case PPC::BI__builtin_divdeu: in isPPC_64Builtin()
62 case PPC::BI__builtin_bpermd: in isPPC_64Builtin()
63 case PPC::BI__builtin_pdepd: in isPPC_64Builtin()
64 case PPC::BI__builtin_pextd: in isPPC_64Builtin()
65 case PPC::BI__builtin_ppc_cdtbcd: in isPPC_64Builtin()
66 case PPC::BI__builtin_ppc_cbcdtd: in isPPC_64Builtin()
67 case PPC::BI__builtin_ppc_addg6s: in isPPC_64Builtin()
68 case PPC::BI__builtin_ppc_ldarx: in isPPC_64Builtin()
69 case PPC::BI__builtin_ppc_stdcx: in isPPC_64Builtin()
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DPPC.cpp33 case clang::PPC::BI__builtin_ppc_ldarx: in emitPPCLoadReserveIntrinsic()
37 case clang::PPC::BI__builtin_ppc_lwarx: in emitPPCLoadReserveIntrinsic()
41 case clang::PPC::BI__builtin_ppc_lharx: in emitPPCLoadReserveIntrinsic()
45 case clang::PPC::BI__builtin_ppc_lbarx: in emitPPCLoadReserveIntrinsic()
224 case PPC::BI__builtin_ppc_get_timebase: in EmitPPCBuiltinExpr()
228 case PPC::BI__builtin_altivec_lvx: in EmitPPCBuiltinExpr()
229 case PPC::BI__builtin_altivec_lvxl: in EmitPPCBuiltinExpr()
230 case PPC::BI__builtin_altivec_lvebx: in EmitPPCBuiltinExpr()
231 case PPC::BI__builtin_altivec_lvehx: in EmitPPCBuiltinExpr()
232 case PPC::BI__builtin_altivec_lvewx: in EmitPPCBuiltinExpr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp104 if (RB->getID() == PPC::GPRRegBankID) { in getRegClass()
106 return &PPC::G8RCRegClass; in getRegClass()
108 return &PPC::GPRCRegClass; in getRegClass()
110 if (RB->getID() == PPC::FPRRegBankID) { in getRegClass()
112 return &PPC::F4RCRegClass; in getRegClass()
114 return &PPC::F8RCRegClass; in getRegClass()
116 if (RB->getID() == PPC::VECRegBankID) { in getRegClass()
118 return &PPC::VSRCRegClass; in getRegClass()
120 if (RB->getID() == PPC::CRRegBankID) { in getRegClass()
122 return &PPC::CRBITRCRegClass; in getRegClass()
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