| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 150 (AM != ISD::POST_INC && AM != ISD::PRE_DEC)) { in selectIndexedLoad()
193 LD->getAddressingMode() != ISD::POST_INC) in selectIndexedProgMemLoad()
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| H A D | AVRISelLowering.cpp | 122 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering()
123 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in AVRTargetLowering()
126 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering()
127 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); in AVRTargetLowering()
1131 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1634 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
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| H A D | BasicTTIImpl.h | 204 return ISD::POST_INC; in getISDIndexedMode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelDAGToDAG.cpp | 306 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD) in isValidIndexedLoad()
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| H A D | MSP430ISelLowering.cpp | 60 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
61 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
1233 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 833 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg()
869 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre()
889 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm()
968 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode3Offset()
1086 if (AM != ISD::POST_INC) in SelectAddrMode6Offset()
1397 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm8Offset()
1465 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm7Offset()
1669 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD || in tryT1IndexedLoad()
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| H A D | ARMISelLowering.cpp | 1140 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); in ARMTargetLowering()
1141 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); in ARMTargetLowering()
19972 AM = ISD::POST_INC; in getPostIndexedAddressParts()
20006 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; in getPostIndexedAddressParts()
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| H A D | ARMInstrMVE.td | 7054 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
7148 …return cast<MaskedStoreSDNode>(N)->isTruncatingStore() && (AM == ISD::POST_INC || AM == ISD::POST_…
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 604 case ISD::POST_INC: return "<post-inc>"; in getIndexedModeName()
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| H A D | DAGCombiner.cpp | 19694 if (getCombineLoadStoreParts(User, ISD::POST_INC, ISD::POST_DEC, IsLoad, in shouldCombineToPostInc()
19720 if (!getCombineLoadStoreParts(N, ISD::POST_INC, ISD::POST_DEC, IsLoad, in getPostIndexedLoadStoreOp()
19823 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB); in SplitIndexingFromLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 838 assert((AM == ISD::PRE_INC || AM == ISD::POST_INC) && in tryIndexedLoad()
841 bool IsPost = AM == ISD::POST_INC; in tryIndexedLoad()
1736 if (Load->getAddressingMode() != ISD::POST_INC) in Select()
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| H A D | RISCVISelLowering.cpp | 1570 for (unsigned im : {ISD::PRE_INC, ISD::POST_INC}) { in RISCVTargetLowering()
1586 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in RISCVTargetLowering()
1587 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in RISCVTargetLowering()
1588 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); in RISCVTargetLowering()
1590 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); in RISCVTargetLowering()
1591 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); in RISCVTargetLowering()
1592 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); in RISCVTargetLowering()
23695 AM = ISD::POST_INC; in getPostIndexedAddressParts()
23717 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 719 AM = ISD::POST_INC; in getPostIndexedAddressParts()
1896 setIndexedLoadAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
1897 setIndexedStoreAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
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| H A D | HexagonISelLoweringHVX.cpp | 195 setIndexedLoadAction(ISD::POST_INC, T, Legal); in initializeHVXLowering()
196 setIndexedStoreAction(ISD::POST_INC, T, Legal); in initializeHVXLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 1482 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
1488 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2119 setIndexedLoadAction(ISD::POST_INC, VT, Legal); in addTypeForNEON()
2120 setIndexedStoreAction(ISD::POST_INC, VT, Legal); in addTypeForNEON()
27231 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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