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Searched refs:PN0 (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstructionCombining.cpp2009 PHINode *PN0, *PN1; in foldBinopWithRecurrence() local
2011 if (!matchSimpleRecurrence(BO0, PN0, Start0, Step0) || !PN0->hasOneUse() || in foldBinopWithRecurrence()
2013 PN0->getParent() != PN1->getParent()) in foldBinopWithRecurrence()
2016 assert(PN0->getNumIncomingValues() == 2 && PN1->getNumIncomingValues() == 2 && in foldBinopWithRecurrence()
2034 auto *NewPN = PHINode::Create(PN0->getType(), PN0->getNumIncomingValues(), in foldBinopWithRecurrence()
2055 for (unsigned I = 0, E = PN0->getNumIncomingValues(); I != E; ++I) { in foldBinopWithRecurrence()
2056 auto *V = PN0->getIncomingValue(I); in foldBinopWithRecurrence()
2057 auto *BB = PN0->getIncomingBlock(I); in foldBinopWithRecurrence()
2076 LLVM_DEBUG(dbgs() << " Combined " << *PN0 << "\n " << *BO0 in foldBinopWithRecurrence()
2081 InsertNewInstWith(NewPN, PN0->getIterator()); in foldBinopWithRecurrence()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1364 if (Reg < AArch64::PN0 || Reg > AArch64::PN15) in printPredicateAsCounter()
1366 O << "pn" << Reg - AArch64::PN0; in printPredicateAsCounter()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td878 def PN0 : AArch64Reg<0, "pn0">, DwarfRegNum<[48]>;
897 def P0 : AArch64Reg<0, "p0", [PN0]>, DwarfRegAlias<PN0>;
H A DAArch64FrameLowering.cpp3201 unsigned PNReg = PReg - AArch64::P0 + AArch64::PN0; in findFreePredicateReg()
H A DAArch64InstrInfo.cpp5118 return (R - AArch64::PN0) + AArch64::P0; in copyPhysReg()
H A DAArch64ISelLowering.cpp12323 return std::make_pair(AArch64::PN0 + V, &AArch64::PNRRegClass); in parseSVERegAsConstraint()
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun9i-a80.dtsi1232 pins = "PN0", "PN1";
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1823 if (Reg >= AArch64::PN0 && Reg <= AArch64::PN15) in addPPRorPNRRegOperands()
1824 Reg = Reg - AArch64::PN0 + AArch64::P0; in addPPRorPNRRegOperands()
1831 MCOperand::createReg((getReg() - AArch64::PN0) + AArch64::P0)); in addPNRasPPRRegOperands()
2857 .Case("pn0", AArch64::PN0) in matchSVEPredicateAsCounterRegName()