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Searched refs:PLLU_BASE (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c396 .base_reg = PLLU_BASE,
510 GATE(0, "pllU_480", "pllU", PLLU_BASE, 22),
511 GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23),
512 GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25),
551 DIV_TB(0, "pllU_out0", "pllU", PLLU_BASE, 16, 5, tegra210_pll_pdiv_tbl),
H A Dtegra210_car.h102 #define PLLU_BASE 0x0c0 macro
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_car.h90 #define PLLU_BASE 0x0c0 macro
H A Dtegra124_car.c246 GATE_PLL(TEGRA124_CLK_PLL_U_480M, "pllU_480", "pllU_out", PLLU_BASE, 22),
H A Dtegra124_clk_pll.c312 .base_reg = PLLU_BASE,