Searched refs:PLL4 (Results 1 – 13 of 13) sorted by relevance
9 #define PLL4 0 macro
11 #define PLL4 0 macro
22 #define PLL4 9 macro
186 #define PLL4 179 macro
41 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
230 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF */
108 <&lcc PLL4>;
136 <&lcc PLL4>;
501 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
690 <&lcc PLL4>;
3375 #define PLL4 0x1618c macro3386 while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9300_get_pll3_sqsum_dvc()
1017 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via