Searched refs:PLL2 (Results 1 – 6 of 6) sorted by relevance
30 For all PLL1, PLL2, ... an optional child node can be used to specify spread49 PLL2 {
30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
127 #define PLL2 118 macro
20 #define PLL2 7 macro
184 #define PLL2 177 macro
196 * that is parent of TIMCLK, PLL1 and PLL2241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */