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Searched refs:PLL1 (Results 1 – 10 of 10) sorted by relevance

/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8960.h126 #define PLL1 117 macro
H A Dstm32mp13-clks.h19 #define PLL1 6 macro
H A Dstm32mp1-clks.h183 #define PLL1 176 macro
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dti,cdce925.txt30 For all PLL1, PLL2, ... an optional child node can be used to specify spread
H A Dst,nomadik.txt30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/davinci/
H A Dpll.txt10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
/freebsd/sys/contrib/device-tree/Bindings/clock/st/
H A Dst,flexgen.txt31 | | |PLL1 | | | | | | | | | |
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dste-nomadik-stn8815.dtsi196 * that is parent of TIMCLK, PLL1 and PLL2
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
/freebsd/sys/contrib/device-tree/src/mips/ingenic/
H A Dgcw0.dts442 * Put high-speed peripherals under PLL1, such that we can change the
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-dhcom-som.dtsi513 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,